swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
113 lines
3.7 KiB
Rust
113 lines
3.7 KiB
Rust
//! # Hardware and Software Reset
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//!
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//! ## Overview
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//! Espressif chips provide four types of reset that occur at different levels,
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//! namely CPU Reset, Core Reset, System Reset, and Chip Reset. All reset types
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//! mentioned above (except Chip Reset) preserve the data stored in internal
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//! memory.
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//!
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//! The Hardware and Software Reset module provides functions for
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//! performing hardware and software resets and includes functions for
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//! retrieving the reset reason and the wakeup cause after a reset.
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//!
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//! The module defines a set of sleep sources (`SleepSource`) that indicate the
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//! source of the wakeup event. It also includes a set of flags (`WakeupReason`)
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//! that represent different wakeup sources and enable/disable wakeup triggers
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//! for specific events.
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use crate::rtc_cntl::SocResetReason;
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/// Source of the wakeup event
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#[derive(Debug, Copy, Clone)]
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pub enum SleepSource {
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/// In case of deep sleep, reset was not caused by exit from deep sleep
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Undefined = 0,
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/// Not a wakeup cause, used to disable all wakeup sources with
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/// esp_sleep_disable_wakeup_source
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All,
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/// Wakeup caused by external signal using RTC_IO
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Ext0,
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/// Wakeup caused by external signal using RTC_CNTL
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Ext1,
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/// Wakeup caused by timer
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Timer,
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/// Wakeup caused by touchpad
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TouchPad,
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/// Wakeup caused by ULP program
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Ulp,
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/// Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3)
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Gpio,
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/// Wakeup caused by UART (light sleep only)
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Uart,
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/// Wakeup caused by WIFI (light sleep only)
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Wifi,
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/// Wakeup caused by COCPU int
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Cocpu,
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/// Wakeup caused by COCPU crash
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CocpuTrapTrig,
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/// Wakeup caused by BT (light sleep only)
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BT,
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}
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bitflags::bitflags! {
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#[allow(unused)]
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pub(crate) struct WakeupReason: u32 {
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const NoSleep = 0;
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#[cfg(pm_support_ext0_wakeup)]
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/// EXT0 GPIO wakeup
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const ExtEvent0Trig = 1 << 0;
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#[cfg(pm_support_ext1_wakeup)]
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/// EXT1 GPIO wakeup
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const ExtEvent1Trig = 1 << 1;
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/// GPIO wakeup (light sleep only)
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const GpioTrigEn = 1 << 2;
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#[cfg(not(any(esp32c6, esp32h2)))]
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/// Timer wakeup
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const TimerTrigEn = 1 << 3;
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#[cfg(any(esp32c6, esp32h2))]
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/// Timer wakeup
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const TimerTrigEn = 1 << 4;
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#[cfg(pm_support_wifi_wakeup)]
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/// MAC wakeup (light sleep only)
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const WifiTrigEn = 1 << 5;
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/// UART0 wakeup (light sleep only)
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const Uart0TrigEn = 1 << 6;
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/// UART1 wakeup (light sleep only)
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const Uart1TrigEn = 1 << 7;
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#[cfg(pm_support_touch_sensor_wakeup)]
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/// Touch wakeup
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const TouchTrigEn = 1 << 8;
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#[cfg(ulp_supported)]
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/// ULP wakeup
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const UlpTrigEn = 1 << 9;
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#[cfg(pm_support_bt_wakeup)]
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/// BT wakeup (light sleep only)
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const BtTrigEn = 1 << 10;
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#[cfg(riscv_coproc_supported)]
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const CocpuTrigEn = 1 << 11;
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#[cfg(riscv_coproc_supported)]
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const CocpuTrapTrigEn = 1 << 13;
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}
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}
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/// Performs a software reset on the chip.
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pub fn software_reset() {
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crate::rom::software_reset();
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}
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/// Performs a software reset on the CPU.
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pub fn software_reset_cpu() {
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crate::rom::software_reset_cpu();
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}
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/// Retrieves the reason for the last reset as a SocResetReason enum value.
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/// Returns `None` if the reset reason cannot be determined.
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pub fn reset_reason() -> Option<SocResetReason> {
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crate::rtc_cntl::reset_reason(crate::Cpu::current())
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}
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/// Retrieves the cause of the last wakeup event as a SleepSource enum value.
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pub fn wakeup_cause() -> SleepSource {
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crate::rtc_cntl::wakeup_cause()
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}
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