swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
81 lines
3.4 KiB
Rust
81 lines
3.4 KiB
Rust
#[doc = "Register `DCXCNT` reader"]
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pub struct R(crate::R<DCXCNT_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<DCXCNT_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl From<crate::R<DCXCNT_SPEC>> for R {
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#[inline(always)]
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fn from(reader: crate::R<DCXCNT_SPEC>) -> Self {
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R(reader)
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}
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}
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#[doc = "Register `DCXCNT` writer"]
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pub struct W(crate::W<DCXCNT_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<DCXCNT_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<DCXCNT_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<DCXCNT_SPEC>) -> Self {
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W(writer)
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}
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}
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#[doc = "Field `DCXCNT` reader - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
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pub type DCXCNT_R = crate::FieldReader<u8, u8>;
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#[doc = "Field `DCXCNT` writer - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
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pub type DCXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCXCNT_SPEC, u8, u8, 4, O>;
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impl R {
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#[doc = "Bits 0:3 - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
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#[inline(always)]
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pub fn dcxcnt(&self) -> DCXCNT_R {
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DCXCNT_R::new((self.bits & 0x0f) as u8)
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}
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}
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impl W {
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#[doc = "Bits 0:3 - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
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#[inline(always)]
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pub fn dcxcnt(&mut self) -> DCXCNT_W<0> {
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DCXCNT_W::new(self)
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "DCX configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcxcnt](index.html) module"]
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pub struct DCXCNT_SPEC;
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impl crate::RegisterSpec for DCXCNT_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [dcxcnt::R](R) reader structure"]
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impl crate::Readable for DCXCNT_SPEC {
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type Reader = R;
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}
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#[doc = "`write(|w| ..)` method takes [dcxcnt::W](W) writer structure"]
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impl crate::Writable for DCXCNT_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets DCXCNT to value 0"]
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impl crate::Resettable for DCXCNT_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
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}
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