swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
168 lines
7.3 KiB
Rust
168 lines
7.3 KiB
Rust
#[doc = "Register `INT_ENA` reader"]
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pub type R = crate::R<INT_ENA_SPEC>;
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#[doc = "Register `INT_ENA` writer"]
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pub type W = crate::W<INT_ENA_SPEC>;
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#[doc = "Field `SLAVE_TRAN_COMP` reader - enable slave transit complete interrupt"]
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pub type SLAVE_TRAN_COMP_R = crate::BitReader;
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#[doc = "Field `SLAVE_TRAN_COMP` writer - enable slave transit complete interrupt"]
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pub type SLAVE_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `ARBITRATION_LOST` reader - enable arbitration lost interrupt"]
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pub type ARBITRATION_LOST_R = crate::BitReader;
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#[doc = "Field `ARBITRATION_LOST` writer - enable arbitration lost interrupt"]
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pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `MASTER_TRAN_COMP` reader - enable master transit complete interrupt"]
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pub type MASTER_TRAN_COMP_R = crate::BitReader;
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#[doc = "Field `MASTER_TRAN_COMP` writer - enable master transit complete interrupt"]
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pub type MASTER_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TRANS_COMPLETE` reader - enable transit complete interrupt"]
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pub type TRANS_COMPLETE_R = crate::BitReader;
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#[doc = "Field `TRANS_COMPLETE` writer - enable transit complete interrupt"]
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pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TIME_OUT` reader - enable time out interrupt"]
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pub type TIME_OUT_R = crate::BitReader;
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#[doc = "Field `TIME_OUT` writer - enable time out interrupt"]
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pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `ACK_ERR` reader - enable eack error interrupt"]
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pub type ACK_ERR_R = crate::BitReader;
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#[doc = "Field `ACK_ERR` writer - enable eack error interrupt"]
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pub type ACK_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RX_DATA` reader - enable receive data interrupt"]
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pub type RX_DATA_R = crate::BitReader;
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#[doc = "Field `RX_DATA` writer - enable receive data interrupt"]
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pub type RX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TX_DATA` reader - enable transit data interrupt"]
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pub type TX_DATA_R = crate::BitReader;
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#[doc = "Field `TX_DATA` writer - enable transit data interrupt"]
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pub type TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `DETECT_START` reader - enable detect start interrupt"]
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pub type DETECT_START_R = crate::BitReader;
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#[doc = "Field `DETECT_START` writer - enable detect start interrupt"]
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pub type DETECT_START_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - enable slave transit complete interrupt"]
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#[inline(always)]
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pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
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SLAVE_TRAN_COMP_R::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - enable arbitration lost interrupt"]
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#[inline(always)]
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pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
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ARBITRATION_LOST_R::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - enable master transit complete interrupt"]
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#[inline(always)]
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pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
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MASTER_TRAN_COMP_R::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - enable transit complete interrupt"]
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#[inline(always)]
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pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
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TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - enable time out interrupt"]
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#[inline(always)]
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pub fn time_out(&self) -> TIME_OUT_R {
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TIME_OUT_R::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 5 - enable eack error interrupt"]
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#[inline(always)]
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pub fn ack_err(&self) -> ACK_ERR_R {
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ACK_ERR_R::new(((self.bits >> 5) & 1) != 0)
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}
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#[doc = "Bit 6 - enable receive data interrupt"]
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#[inline(always)]
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pub fn rx_data(&self) -> RX_DATA_R {
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RX_DATA_R::new(((self.bits >> 6) & 1) != 0)
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}
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#[doc = "Bit 7 - enable transit data interrupt"]
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#[inline(always)]
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pub fn tx_data(&self) -> TX_DATA_R {
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TX_DATA_R::new(((self.bits >> 7) & 1) != 0)
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}
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#[doc = "Bit 8 - enable detect start interrupt"]
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#[inline(always)]
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pub fn detect_start(&self) -> DETECT_START_R {
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DETECT_START_R::new(((self.bits >> 8) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("INT_ENA")
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.field("slave_tran_comp", &self.slave_tran_comp())
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.field("arbitration_lost", &self.arbitration_lost())
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.field("master_tran_comp", &self.master_tran_comp())
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.field("trans_complete", &self.trans_complete())
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.field("time_out", &self.time_out())
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.field("ack_err", &self.ack_err())
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.field("rx_data", &self.rx_data())
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.field("tx_data", &self.tx_data())
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.field("detect_start", &self.detect_start())
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - enable slave transit complete interrupt"]
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#[inline(always)]
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pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
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SLAVE_TRAN_COMP_W::new(self, 0)
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}
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#[doc = "Bit 1 - enable arbitration lost interrupt"]
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#[inline(always)]
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pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
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ARBITRATION_LOST_W::new(self, 1)
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}
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#[doc = "Bit 2 - enable master transit complete interrupt"]
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#[inline(always)]
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pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
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MASTER_TRAN_COMP_W::new(self, 2)
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}
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#[doc = "Bit 3 - enable transit complete interrupt"]
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#[inline(always)]
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pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
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TRANS_COMPLETE_W::new(self, 3)
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}
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#[doc = "Bit 4 - enable time out interrupt"]
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#[inline(always)]
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pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
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TIME_OUT_W::new(self, 4)
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}
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#[doc = "Bit 5 - enable eack error interrupt"]
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#[inline(always)]
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pub fn ack_err(&mut self) -> ACK_ERR_W<INT_ENA_SPEC> {
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ACK_ERR_W::new(self, 5)
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}
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#[doc = "Bit 6 - enable receive data interrupt"]
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#[inline(always)]
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pub fn rx_data(&mut self) -> RX_DATA_W<INT_ENA_SPEC> {
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RX_DATA_W::new(self, 6)
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}
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#[doc = "Bit 7 - enable transit data interrupt"]
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#[inline(always)]
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pub fn tx_data(&mut self) -> TX_DATA_W<INT_ENA_SPEC> {
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TX_DATA_W::new(self, 7)
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}
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#[doc = "Bit 8 - enable detect start interrupt"]
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#[inline(always)]
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pub fn detect_start(&mut self) -> DETECT_START_W<INT_ENA_SPEC> {
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DETECT_START_W::new(self, 8)
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}
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}
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#[doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct INT_ENA_SPEC;
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impl crate::RegisterSpec for INT_ENA_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
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impl crate::Readable for INT_ENA_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
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impl crate::Writable for INT_ENA_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets INT_ENA to value 0"]
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impl crate::Resettable for INT_ENA_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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