swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
63 lines
2.9 KiB
Rust
63 lines
2.9 KiB
Rust
#[doc = "Register `SIGMADELTA%s` reader"]
|
|
pub type R = crate::R<SIGMADELTA_SPEC>;
|
|
#[doc = "Register `SIGMADELTA%s` writer"]
|
|
pub type W = crate::W<SIGMADELTA_SPEC>;
|
|
#[doc = "Field `IN` reader - This field is used to configure the duty cycle of sigma delta modulation output."]
|
|
pub type IN_R = crate::FieldReader;
|
|
#[doc = "Field `IN` writer - This field is used to configure the duty cycle of sigma delta modulation output."]
|
|
pub type IN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
|
|
#[doc = "Field `PRESCALE` reader - This field is used to set a divider value to divide APB clock."]
|
|
pub type PRESCALE_R = crate::FieldReader;
|
|
#[doc = "Field `PRESCALE` writer - This field is used to set a divider value to divide APB clock."]
|
|
pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
|
|
impl R {
|
|
#[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
|
|
#[inline(always)]
|
|
pub fn in_(&self) -> IN_R {
|
|
IN_R::new((self.bits & 0xff) as u8)
|
|
}
|
|
#[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."]
|
|
#[inline(always)]
|
|
pub fn prescale(&self) -> PRESCALE_R {
|
|
PRESCALE_R::new(((self.bits >> 8) & 0xff) as u8)
|
|
}
|
|
}
|
|
#[cfg(feature = "impl-register-debug")]
|
|
impl core::fmt::Debug for R {
|
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
|
f.debug_struct("SIGMADELTA")
|
|
.field("in_", &self.in_())
|
|
.field("prescale", &self.prescale())
|
|
.finish()
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
|
|
#[inline(always)]
|
|
pub fn in_(&mut self) -> IN_W<SIGMADELTA_SPEC> {
|
|
IN_W::new(self, 0)
|
|
}
|
|
#[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."]
|
|
#[inline(always)]
|
|
pub fn prescale(&mut self) -> PRESCALE_W<SIGMADELTA_SPEC> {
|
|
PRESCALE_W::new(self, 8)
|
|
}
|
|
}
|
|
#[doc = "Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::Reg::read) this register and get [`sigmadelta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigmadelta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
|
pub struct SIGMADELTA_SPEC;
|
|
impl crate::RegisterSpec for SIGMADELTA_SPEC {
|
|
type Ux = u32;
|
|
}
|
|
#[doc = "`read()` method returns [`sigmadelta::R`](R) reader structure"]
|
|
impl crate::Readable for SIGMADELTA_SPEC {}
|
|
#[doc = "`write(|w| ..)` method takes [`sigmadelta::W`](W) writer structure"]
|
|
impl crate::Writable for SIGMADELTA_SPEC {
|
|
type Safety = crate::Unsafe;
|
|
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
|
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
|
}
|
|
#[doc = "`reset()` method sets SIGMADELTA%s to value 0xff00"]
|
|
impl crate::Resettable for SIGMADELTA_SPEC {
|
|
const RESET_VALUE: u32 = 0xff00;
|
|
}
|