swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
63 lines
2.9 KiB
Rust
63 lines
2.9 KiB
Rust
#[doc = "Register `FIFO_ST` reader"]
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pub type R = crate::R<FIFO_ST_SPEC>;
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#[doc = "Field `RXFIFO_RADDR` reader - This is the offset address of the APB reading from rxfifo"]
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pub type RXFIFO_RADDR_R = crate::FieldReader;
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#[doc = "Field `RXFIFO_WADDR` reader - This is the offset address of i2c module receiving data and writing to rxfifo."]
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pub type RXFIFO_WADDR_R = crate::FieldReader;
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#[doc = "Field `TXFIFO_RADDR` reader - This is the offset address of i2c module reading from txfifo."]
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pub type TXFIFO_RADDR_R = crate::FieldReader;
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#[doc = "Field `TXFIFO_WADDR` reader - This is the offset address of APB bus writing to txfifo."]
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pub type TXFIFO_WADDR_R = crate::FieldReader;
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#[doc = "Field `SLAVE_RW_POINT` reader - The received data in I2C slave mode."]
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pub type SLAVE_RW_POINT_R = crate::FieldReader;
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impl R {
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#[doc = "Bits 0:4 - This is the offset address of the APB reading from rxfifo"]
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#[inline(always)]
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pub fn rxfifo_raddr(&self) -> RXFIFO_RADDR_R {
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RXFIFO_RADDR_R::new((self.bits & 0x1f) as u8)
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}
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#[doc = "Bits 5:9 - This is the offset address of i2c module receiving data and writing to rxfifo."]
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#[inline(always)]
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pub fn rxfifo_waddr(&self) -> RXFIFO_WADDR_R {
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RXFIFO_WADDR_R::new(((self.bits >> 5) & 0x1f) as u8)
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}
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#[doc = "Bits 10:14 - This is the offset address of i2c module reading from txfifo."]
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#[inline(always)]
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pub fn txfifo_raddr(&self) -> TXFIFO_RADDR_R {
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TXFIFO_RADDR_R::new(((self.bits >> 10) & 0x1f) as u8)
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}
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#[doc = "Bits 15:19 - This is the offset address of APB bus writing to txfifo."]
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#[inline(always)]
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pub fn txfifo_waddr(&self) -> TXFIFO_WADDR_R {
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TXFIFO_WADDR_R::new(((self.bits >> 15) & 0x1f) as u8)
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}
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#[doc = "Bits 22:29 - The received data in I2C slave mode."]
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#[inline(always)]
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pub fn slave_rw_point(&self) -> SLAVE_RW_POINT_R {
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SLAVE_RW_POINT_R::new(((self.bits >> 22) & 0xff) as u8)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("FIFO_ST")
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.field("rxfifo_raddr", &self.rxfifo_raddr())
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.field("rxfifo_waddr", &self.rxfifo_waddr())
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.field("txfifo_raddr", &self.txfifo_raddr())
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.field("txfifo_waddr", &self.txfifo_waddr())
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.field("slave_rw_point", &self.slave_rw_point())
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.finish()
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}
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}
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#[doc = "FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct FIFO_ST_SPEC;
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impl crate::RegisterSpec for FIFO_ST_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"]
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impl crate::Readable for FIFO_ST_SPEC {}
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#[doc = "`reset()` method sets FIFO_ST to value 0"]
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impl crate::Resettable for FIFO_ST_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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