swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
48 lines
2.5 KiB
Rust
48 lines
2.5 KiB
Rust
#[doc = "Register `SCL_STOP_SETUP` reader"]
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pub type R = crate::R<SCL_STOP_SETUP_SPEC>;
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#[doc = "Register `SCL_STOP_SETUP` writer"]
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pub type W = crate::W<SCL_STOP_SETUP_SPEC>;
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#[doc = "Field `TIME` reader - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
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pub type TIME_R = crate::FieldReader<u16>;
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#[doc = "Field `TIME` writer - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
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pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
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impl R {
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#[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
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#[inline(always)]
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pub fn time(&self) -> TIME_R {
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TIME_R::new((self.bits & 0x01ff) as u16)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("SCL_STOP_SETUP")
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.field("time", &self.time())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
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#[inline(always)]
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pub fn time(&mut self) -> TIME_W<SCL_STOP_SETUP_SPEC> {
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TIME_W::new(self, 0)
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}
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}
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#[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct SCL_STOP_SETUP_SPEC;
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impl crate::RegisterSpec for SCL_STOP_SETUP_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`scl_stop_setup::R`](R) reader structure"]
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impl crate::Readable for SCL_STOP_SETUP_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`scl_stop_setup::W`](W) writer structure"]
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impl crate::Writable for SCL_STOP_SETUP_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets SCL_STOP_SETUP to value 0x08"]
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impl crate::Resettable for SCL_STOP_SETUP_SPEC {
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const RESET_VALUE: u32 = 0x08;
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}
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