swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
63 lines
2.8 KiB
Rust
63 lines
2.8 KiB
Rust
#[doc = "Register `SAR_MEAS2_MUX` reader"]
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pub type R = crate::R<SAR_MEAS2_MUX_SPEC>;
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#[doc = "Register `SAR_MEAS2_MUX` writer"]
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pub type W = crate::W<SAR_MEAS2_MUX_SPEC>;
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#[doc = "Field `SAR2_PWDET_CCT` reader - SAR2_PWDET_CCT"]
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pub type SAR2_PWDET_CCT_R = crate::FieldReader;
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#[doc = "Field `SAR2_PWDET_CCT` writer - SAR2_PWDET_CCT"]
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pub type SAR2_PWDET_CCT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
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#[doc = "Field `SAR2_RTC_FORCE` reader - in sleep, force to use rtc to control ADC"]
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pub type SAR2_RTC_FORCE_R = crate::BitReader;
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#[doc = "Field `SAR2_RTC_FORCE` writer - in sleep, force to use rtc to control ADC"]
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pub type SAR2_RTC_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bits 28:30 - SAR2_PWDET_CCT"]
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#[inline(always)]
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pub fn sar2_pwdet_cct(&self) -> SAR2_PWDET_CCT_R {
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SAR2_PWDET_CCT_R::new(((self.bits >> 28) & 7) as u8)
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}
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#[doc = "Bit 31 - in sleep, force to use rtc to control ADC"]
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#[inline(always)]
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pub fn sar2_rtc_force(&self) -> SAR2_RTC_FORCE_R {
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SAR2_RTC_FORCE_R::new(((self.bits >> 31) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("SAR_MEAS2_MUX")
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.field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
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.field("sar2_rtc_force", &self.sar2_rtc_force())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 28:30 - SAR2_PWDET_CCT"]
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#[inline(always)]
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pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W<SAR_MEAS2_MUX_SPEC> {
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SAR2_PWDET_CCT_W::new(self, 28)
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}
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#[doc = "Bit 31 - in sleep, force to use rtc to control ADC"]
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#[inline(always)]
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pub fn sar2_rtc_force(&mut self) -> SAR2_RTC_FORCE_W<SAR_MEAS2_MUX_SPEC> {
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SAR2_RTC_FORCE_W::new(self, 31)
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}
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}
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#[doc = "configure saradc2 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas2_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas2_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct SAR_MEAS2_MUX_SPEC;
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impl crate::RegisterSpec for SAR_MEAS2_MUX_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`sar_meas2_mux::R`](R) reader structure"]
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impl crate::Readable for SAR_MEAS2_MUX_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`sar_meas2_mux::W`](W) writer structure"]
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impl crate::Writable for SAR_MEAS2_MUX_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets SAR_MEAS2_MUX to value 0"]
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impl crate::Resettable for SAR_MEAS2_MUX_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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