swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
62 lines
2.9 KiB
Plaintext
62 lines
2.9 KiB
Plaintext
/* This memory map assumes the flash cache is on;
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the blocks used are excluded from the various memory ranges
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see: https://github.com/espressif/esp-idf/blob/5b1189570025ba027f2ff6c2d91f6ffff3809cc2/components/heap/port/esp32/memory_layout.c
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for details
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*/
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/* override entry point */
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ENTRY(ESP32Reset)
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INCLUDE "memory_extras.x"
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/* Specify main memory areas */
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MEMORY
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{
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reserved_cache_seg : ORIGIN = 0x40070000, len = 64k /* SRAM0; reserved for usage as flash cache*/
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vectors_seg ( RX ) : ORIGIN = 0x40080000, len = 1k /* SRAM0 */
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iram_seg ( RX ) : ORIGIN = 0x40080400, len = 128k-0x400 /* SRAM0 */
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reserved_for_rom_seg : ORIGIN = 0x3FFAE000, len = 8k /* SRAM2; reserved for usage by the ROM */
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dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM, len = 176k - RESERVE_DRAM /* SRAM2+1; first 64kB used by BT if enable */
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/*
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* The following values come from the heap allocator in esp-idf: https://github.com/espressif/esp-idf/blob/ab63aaa4a24a05904da2862d627f3987ecbeafd0/components/heap/port/esp32/memory_layout.c#L137-L157
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* The segment dram2_seg after the rom data space is not mentioned in the esp32 linker scripts in esp-idf, instead the space after is used as heap space.
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* It seems not all rom data space is reserved, but only "core"/"important" ROM functions that may be called after booting from ROM.
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*/
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reserved_rom_data_pro : ORIGIN = 0x3ffe0000, len = 1088
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reserved_rom_data_app : ORIGIN = 0x3ffe3f20, len = 1072
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/*
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* The following values are derived from the __stack and _stack_sentry values from ROM.
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* They represent the stacks used for each core setup by ROM code. In theory both of these
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* can be reclaimed once both cores are running, but for now we play it safe and reserve them both.
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*/
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reserved_rom_stack_pro : ORIGIN = 0x3ffe1320, len = 11264
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reserved_rom_stack_app : ORIGIN = 0x3ffe5230, len = 11264
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dram2_seg : ORIGIN = 0x3ffe7e30, len = 98767 /* the rest of DRAM after the rom data segments and rom stacks in the middle */
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/* external flash
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The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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irom_seg ( RX ) : ORIGIN = 0x400D0020, len = 3M - 0x20
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drom_seg ( R ) : ORIGIN = 0x3F400020, len = 4M - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
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rtc_fast_iram_seg(RWX) : ORIGIN = 0x400C0000, len = 8k
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/* RTC fast memory (same block as above), viewed from data bus. Only for core 0 (PRO_CPU) */
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rtc_fast_dram_seg(RW) : ORIGIN = 0x3FF80000, len = 8k
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : ORIGIN = 0x50000000, len = 8k
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}
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