swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
35 lines
1.3 KiB
Plaintext
35 lines
1.3 KiB
Plaintext
MEMORY
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{
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/* MEMORY_MAP = [
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[0x00000000, 0x00010000, "PADDING"],
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[0x42800000, 0x43000000, "DROM"],
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[0x40800000, 0x40850000, "RAM"],
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[0x40800000, 0x40850000, "BYTE_ACCESSIBLE"],
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[0x4001С400, 0x40020000, "DROM_MASK"],
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[0x40000000, 0x4001С400, "ROM_MASK"],
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[0x42000000, 0x42800000, "ROM"],
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[0x40800000, 0x40850000, "RAM"],
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[0x50000000, 0x50001000, "RTC_RAM"],
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[0x50000000, 0x50001000, "RTC_RAM"],
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[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
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] */
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/* 320K of on soc RAM, 16K reserved for cache */
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/* Instruction and Data RAM
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0x4083EFD0 = 2nd stage bootloader iram_loader_seg start address
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see https://github.com/espressif/esp-idf/blob/03414a15508036c8fc0f51642aed7a264e9527df/components/esp_system/ld/esp32h2/memory.ld.in#L26
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*/
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RAM : ORIGIN = 0x40800000, LENGTH = 0x3EFD0
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/* memory available after the 2nd stage bootloader is finished */
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dram2_seg ( RW ) : ORIGIN = ORIGIN(RAM) + LENGTH(RAM), len = 0x4084fee0 - (ORIGIN(RAM) + LENGTH(RAM))
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/* External flash */
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/* Instruction and Data ROM */
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ROM : ORIGIN = 0x42000000, LENGTH = 0x400000
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/* RTC fast memory (executable). Persists over deep sleep. */
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RTC_FAST : ORIGIN = 0x50000000, LENGTH = 16K /*- ESP_BOOTLOADER_RESERVE_RTC*/
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}
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