swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
71 lines
2.7 KiB
Rust
71 lines
2.7 KiB
Rust
#[doc = "Register `INT_ST` reader"]
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pub type R = crate::R<INT_ST_SPEC>;
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#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
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pub type THRES1_LOW_R = crate::BitReader;
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#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
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pub type THRES0_LOW_R = crate::BitReader;
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#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
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pub type THRES1_HIGH_R = crate::BitReader;
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#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
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pub type THRES0_HIGH_R = crate::BitReader;
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#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
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pub type ADC2_DONE_R = crate::BitReader;
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#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
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pub type ADC1_DONE_R = crate::BitReader;
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impl R {
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#[doc = "Bit 26 - interrupt of thres1 low"]
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#[inline(always)]
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pub fn thres1_low(&self) -> THRES1_LOW_R {
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THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
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}
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#[doc = "Bit 27 - interrupt of thres0 low"]
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#[inline(always)]
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pub fn thres0_low(&self) -> THRES0_LOW_R {
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THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
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}
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#[doc = "Bit 28 - interrupt of thres1 high"]
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#[inline(always)]
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pub fn thres1_high(&self) -> THRES1_HIGH_R {
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THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
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}
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#[doc = "Bit 29 - interrupt of thres0 high"]
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#[inline(always)]
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pub fn thres0_high(&self) -> THRES0_HIGH_R {
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THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
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}
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#[doc = "Bit 30 - interrupt of sar2 done"]
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#[inline(always)]
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pub fn adc2_done(&self) -> ADC2_DONE_R {
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ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
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}
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#[doc = "Bit 31 - interrupt of sar1 done"]
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#[inline(always)]
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pub fn adc1_done(&self) -> ADC1_DONE_R {
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ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("INT_ST")
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.field("thres1_low", &self.thres1_low())
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.field("thres0_low", &self.thres0_low())
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.field("thres1_high", &self.thres1_high())
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.field("thres0_high", &self.thres0_high())
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.field("adc2_done", &self.adc2_done())
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.field("adc1_done", &self.adc1_done())
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.finish()
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}
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}
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#[doc = "state of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct INT_ST_SPEC;
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impl crate::RegisterSpec for INT_ST_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
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impl crate::Readable for INT_ST_SPEC {}
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#[doc = "`reset()` method sets INT_ST to value 0"]
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impl crate::Resettable for INT_ST_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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