swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
63 lines
3.4 KiB
Rust
63 lines
3.4 KiB
Rust
#[doc = "Register `DCACHE_PRELOCK_CTRL` reader"]
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pub type R = crate::R<DCACHE_PRELOCK_CTRL_SPEC>;
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#[doc = "Register `DCACHE_PRELOCK_CTRL` writer"]
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pub type W = crate::W<DCACHE_PRELOCK_CTRL_SPEC>;
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#[doc = "Field `DCACHE_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function."]
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pub type DCACHE_PRELOCK_SCT0_EN_R = crate::BitReader;
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#[doc = "Field `DCACHE_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function."]
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pub type DCACHE_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `DCACHE_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function."]
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pub type DCACHE_PRELOCK_SCT1_EN_R = crate::BitReader;
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#[doc = "Field `DCACHE_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function."]
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pub type DCACHE_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
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#[inline(always)]
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pub fn dcache_prelock_sct0_en(&self) -> DCACHE_PRELOCK_SCT0_EN_R {
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DCACHE_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
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#[inline(always)]
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pub fn dcache_prelock_sct1_en(&self) -> DCACHE_PRELOCK_SCT1_EN_R {
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DCACHE_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("DCACHE_PRELOCK_CTRL")
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.field("dcache_prelock_sct0_en", &self.dcache_prelock_sct0_en())
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.field("dcache_prelock_sct1_en", &self.dcache_prelock_sct1_en())
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
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#[inline(always)]
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pub fn dcache_prelock_sct0_en(&mut self) -> DCACHE_PRELOCK_SCT0_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
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DCACHE_PRELOCK_SCT0_EN_W::new(self, 0)
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}
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#[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
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#[inline(always)]
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pub fn dcache_prelock_sct1_en(&mut self) -> DCACHE_PRELOCK_SCT1_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
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DCACHE_PRELOCK_SCT1_EN_W::new(self, 1)
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}
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}
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#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct DCACHE_PRELOCK_CTRL_SPEC;
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impl crate::RegisterSpec for DCACHE_PRELOCK_CTRL_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`dcache_prelock_ctrl::R`](R) reader structure"]
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impl crate::Readable for DCACHE_PRELOCK_CTRL_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`dcache_prelock_ctrl::W`](W) writer structure"]
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impl crate::Writable for DCACHE_PRELOCK_CTRL_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets DCACHE_PRELOCK_CTRL to value 0"]
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impl crate::Resettable for DCACHE_PRELOCK_CTRL_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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