swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
48 lines
3.2 KiB
Rust
48 lines
3.2 KiB
Rust
#[doc = "Register `EP1` reader"]
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pub type R = crate::R<EP1_SPEC>;
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#[doc = "Register `EP1` writer"]
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pub type W = crate::W<EP1_SPEC>;
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#[doc = "Field `RDWR_BYTE` reader - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
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pub type RDWR_BYTE_R = crate::FieldReader;
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#[doc = "Field `RDWR_BYTE` writer - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
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pub type RDWR_BYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
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impl R {
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#[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
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#[inline(always)]
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pub fn rdwr_byte(&self) -> RDWR_BYTE_R {
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RDWR_BYTE_R::new((self.bits & 0xff) as u8)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("EP1")
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.field("rdwr_byte", &self.rdwr_byte())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
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#[inline(always)]
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pub fn rdwr_byte(&mut self) -> RDWR_BYTE_W<EP1_SPEC> {
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RDWR_BYTE_W::new(self, 0)
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}
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}
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#[doc = "Endpoint 1 FIFO register\n\nYou can [`read`](crate::Reg::read) this register and get [`ep1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct EP1_SPEC;
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impl crate::RegisterSpec for EP1_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`ep1::R`](R) reader structure"]
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impl crate::Readable for EP1_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`ep1::W`](W) writer structure"]
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impl crate::Writable for EP1_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets EP1 to value 0"]
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impl crate::Resettable for EP1_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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