swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
247 lines
7.5 KiB
Rust
247 lines
7.5 KiB
Rust
#[doc = "Register `CONFIG` reader"]
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pub struct R(crate::R<CONFIG_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<CONFIG_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl From<crate::R<CONFIG_SPEC>> for R {
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#[inline(always)]
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fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
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R(reader)
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}
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}
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#[doc = "Register `CONFIG` writer"]
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pub struct W(crate::W<CONFIG_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<CONFIG_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<CONFIG_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
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W(writer)
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}
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}
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#[doc = "Field `ORDER` reader - Bit order"]
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pub type ORDER_R = crate::BitReader<ORDER_A>;
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#[doc = "Bit order\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ORDER_A {
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#[doc = "0: Most significant bit shifted out first"]
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MSB_FIRST = 0,
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#[doc = "1: Least significant bit shifted out first"]
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LSB_FIRST = 1,
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}
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impl From<ORDER_A> for bool {
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#[inline(always)]
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fn from(variant: ORDER_A) -> Self {
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variant as u8 != 0
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}
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}
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impl ORDER_R {
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#[doc = "Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> ORDER_A {
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match self.bits {
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false => ORDER_A::MSB_FIRST,
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true => ORDER_A::LSB_FIRST,
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}
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}
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#[doc = "Checks if the value of the field is `MSB_FIRST`"]
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#[inline(always)]
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pub fn is_msb_first(&self) -> bool {
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*self == ORDER_A::MSB_FIRST
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}
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#[doc = "Checks if the value of the field is `LSB_FIRST`"]
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#[inline(always)]
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pub fn is_lsb_first(&self) -> bool {
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*self == ORDER_A::LSB_FIRST
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}
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}
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#[doc = "Field `ORDER` writer - Bit order"]
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pub type ORDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ORDER_A, O>;
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impl<'a, const O: u8> ORDER_W<'a, O> {
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#[doc = "Most significant bit shifted out first"]
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#[inline(always)]
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pub fn msb_first(self) -> &'a mut W {
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self.variant(ORDER_A::MSB_FIRST)
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}
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#[doc = "Least significant bit shifted out first"]
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#[inline(always)]
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pub fn lsb_first(self) -> &'a mut W {
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self.variant(ORDER_A::LSB_FIRST)
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}
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}
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#[doc = "Field `CPHA` reader - Serial clock (SCK) phase"]
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pub type CPHA_R = crate::BitReader<CPHA_A>;
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#[doc = "Serial clock (SCK) phase\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CPHA_A {
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#[doc = "0: Sample on leading edge of clock, shift serial data on trailing edge"]
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LEADING = 0,
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#[doc = "1: Sample on trailing edge of clock, shift serial data on leading edge"]
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TRAILING = 1,
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}
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impl From<CPHA_A> for bool {
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#[inline(always)]
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fn from(variant: CPHA_A) -> Self {
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variant as u8 != 0
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}
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}
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impl CPHA_R {
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#[doc = "Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> CPHA_A {
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match self.bits {
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false => CPHA_A::LEADING,
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true => CPHA_A::TRAILING,
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}
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}
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#[doc = "Checks if the value of the field is `LEADING`"]
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#[inline(always)]
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pub fn is_leading(&self) -> bool {
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*self == CPHA_A::LEADING
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}
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#[doc = "Checks if the value of the field is `TRAILING`"]
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#[inline(always)]
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pub fn is_trailing(&self) -> bool {
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*self == CPHA_A::TRAILING
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}
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}
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#[doc = "Field `CPHA` writer - Serial clock (SCK) phase"]
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pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPHA_A, O>;
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impl<'a, const O: u8> CPHA_W<'a, O> {
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#[doc = "Sample on leading edge of clock, shift serial data on trailing edge"]
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#[inline(always)]
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pub fn leading(self) -> &'a mut W {
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self.variant(CPHA_A::LEADING)
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}
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#[doc = "Sample on trailing edge of clock, shift serial data on leading edge"]
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#[inline(always)]
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pub fn trailing(self) -> &'a mut W {
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self.variant(CPHA_A::TRAILING)
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}
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}
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#[doc = "Field `CPOL` reader - Serial clock (SCK) polarity"]
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pub type CPOL_R = crate::BitReader<CPOL_A>;
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#[doc = "Serial clock (SCK) polarity\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CPOL_A {
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#[doc = "0: Active high"]
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ACTIVE_HIGH = 0,
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#[doc = "1: Active low"]
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ACTIVE_LOW = 1,
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}
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impl From<CPOL_A> for bool {
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#[inline(always)]
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fn from(variant: CPOL_A) -> Self {
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variant as u8 != 0
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}
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}
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impl CPOL_R {
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#[doc = "Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> CPOL_A {
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match self.bits {
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false => CPOL_A::ACTIVE_HIGH,
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true => CPOL_A::ACTIVE_LOW,
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}
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}
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#[doc = "Checks if the value of the field is `ACTIVE_HIGH`"]
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#[inline(always)]
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pub fn is_active_high(&self) -> bool {
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*self == CPOL_A::ACTIVE_HIGH
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}
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#[doc = "Checks if the value of the field is `ACTIVE_LOW`"]
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#[inline(always)]
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pub fn is_active_low(&self) -> bool {
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*self == CPOL_A::ACTIVE_LOW
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}
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}
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#[doc = "Field `CPOL` writer - Serial clock (SCK) polarity"]
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pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPOL_A, O>;
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impl<'a, const O: u8> CPOL_W<'a, O> {
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#[doc = "Active high"]
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#[inline(always)]
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pub fn active_high(self) -> &'a mut W {
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self.variant(CPOL_A::ACTIVE_HIGH)
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}
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#[doc = "Active low"]
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#[inline(always)]
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pub fn active_low(self) -> &'a mut W {
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self.variant(CPOL_A::ACTIVE_LOW)
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}
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}
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impl R {
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#[doc = "Bit 0 - Bit order"]
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#[inline(always)]
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pub fn order(&self) -> ORDER_R {
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ORDER_R::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - Serial clock (SCK) phase"]
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#[inline(always)]
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pub fn cpha(&self) -> CPHA_R {
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CPHA_R::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - Serial clock (SCK) polarity"]
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#[inline(always)]
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pub fn cpol(&self) -> CPOL_R {
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CPOL_R::new(((self.bits >> 2) & 1) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Bit order"]
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#[inline(always)]
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pub fn order(&mut self) -> ORDER_W<0> {
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ORDER_W::new(self)
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}
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#[doc = "Bit 1 - Serial clock (SCK) phase"]
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#[inline(always)]
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pub fn cpha(&mut self) -> CPHA_W<1> {
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CPHA_W::new(self)
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}
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#[doc = "Bit 2 - Serial clock (SCK) polarity"]
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#[inline(always)]
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pub fn cpol(&mut self) -> CPOL_W<2> {
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CPOL_W::new(self)
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
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pub struct CONFIG_SPEC;
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impl crate::RegisterSpec for CONFIG_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [config::R](R) reader structure"]
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impl crate::Readable for CONFIG_SPEC {
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type Reader = R;
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}
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#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
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impl crate::Writable for CONFIG_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets CONFIG to value 0"]
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impl crate::Resettable for CONFIG_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
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}
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