swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
75 lines
2.2 KiB
Rust
75 lines
2.2 KiB
Rust
use strum::FromRepr;
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use crate::{
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peripherals::RTC_CNTL,
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rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
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};
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pub(crate) fn init() {}
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pub(crate) fn configure_clock() {
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RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m);
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let cal_val = loop {
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RtcClock::set_slow_freq(RtcSlowClock::RtcSlowClockRtc);
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let res = RtcClock::calibrate(RtcCalSel::RtcCalRtcMux, 1024);
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if res != 0 {
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break res;
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}
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};
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unsafe {
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let rtc_cntl = &*RTC_CNTL::ptr();
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rtc_cntl.store1().write(|w| w.bits(cal_val));
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}
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}
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// Terminology:
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//
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// CPU Reset: Reset CPU core only, once reset done, CPU will execute from
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// reset vector
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// Core Reset: Reset the whole digital system except RTC sub-system
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// System Reset: Reset the whole digital system, including RTC sub-system
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// Chip Reset: Reset the whole chip, including the analog part
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#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
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/// SOC Reset Reason.
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pub enum SocResetReason {
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/// Power on reset
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ChipPowerOn = 0x01,
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/// Software resets the digital core
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CoreSw = 0x03,
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/// Deep sleep reset the digital core
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CoreDeepSleep = 0x05,
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/// SDIO module resets the digital core
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CoreSdio = 0x06,
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/// Main watch dog 0 resets digital core
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CoreMwdt0 = 0x07,
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/// Main watch dog 1 resets digital core
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CoreMwdt1 = 0x08,
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/// RTC watch dog resets digital core
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CoreRtcWdt = 0x09,
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/// Main watch dog 0 resets CPU
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///
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/// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
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/// same values.
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CpuMwdt0 = 0x0B,
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/// Software resets CPU
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///
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/// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
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/// values.
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Cpu0Sw = 0x0C,
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/// RTC watch dog resets CPU
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///
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/// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
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/// the same values.
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Cpu0RtcWdt = 0x0D,
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/// CPU0 resets CPU1 by DPORT_APPCPU_RESETTING
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Cpu1Cpu0 = 0x0E,
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/// Reset when the VDD voltage is not stable
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SysBrownOut = 0x0F,
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/// RTC watch dog resets digital core and rtc module
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SysRtcWdt = 0x10,
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}
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