swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
67 lines
2.8 KiB
Rust
67 lines
2.8 KiB
Rust
#[doc = r"Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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_reserved0: [u8; 0x0504],
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#[doc = "0x504 - Write GPIO port"]
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pub out: OUT,
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#[doc = "0x508 - Set individual bits in GPIO port"]
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pub outset: OUTSET,
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#[doc = "0x50c - Clear individual bits in GPIO port"]
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pub outclr: OUTCLR,
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#[doc = "0x510 - Read GPIO port"]
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pub in_: IN,
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#[doc = "0x514 - Direction of GPIO pins"]
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pub dir: DIR,
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#[doc = "0x518 - DIR set register"]
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pub dirset: DIRSET,
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#[doc = "0x51c - DIR clear register"]
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pub dirclr: DIRCLR,
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#[doc = "0x520 - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF\\[n\\].SENSE registers"]
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pub latch: LATCH,
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#[doc = "0x524 - Select between default DETECT signal behaviour and LDETECT mode"]
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pub detectmode: DETECTMODE,
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_reserved9: [u8; 0x01d8],
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#[doc = "0x700..0x780 - Description collection\\[n\\]: Configuration of GPIO pins"]
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pub pin_cnf: [PIN_CNF; 32],
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}
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#[doc = "OUT (rw) register accessor: an alias for `Reg<OUT_SPEC>`"]
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pub type OUT = crate::Reg<out::OUT_SPEC>;
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#[doc = "Write GPIO port"]
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pub mod out;
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#[doc = "OUTSET (rw) register accessor: an alias for `Reg<OUTSET_SPEC>`"]
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pub type OUTSET = crate::Reg<outset::OUTSET_SPEC>;
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#[doc = "Set individual bits in GPIO port"]
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pub mod outset;
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#[doc = "OUTCLR (rw) register accessor: an alias for `Reg<OUTCLR_SPEC>`"]
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pub type OUTCLR = crate::Reg<outclr::OUTCLR_SPEC>;
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#[doc = "Clear individual bits in GPIO port"]
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pub mod outclr;
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#[doc = "IN (r) register accessor: an alias for `Reg<IN_SPEC>`"]
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pub type IN = crate::Reg<in_::IN_SPEC>;
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#[doc = "Read GPIO port"]
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pub mod in_;
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#[doc = "DIR (rw) register accessor: an alias for `Reg<DIR_SPEC>`"]
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pub type DIR = crate::Reg<dir::DIR_SPEC>;
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#[doc = "Direction of GPIO pins"]
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pub mod dir;
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#[doc = "DIRSET (rw) register accessor: an alias for `Reg<DIRSET_SPEC>`"]
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pub type DIRSET = crate::Reg<dirset::DIRSET_SPEC>;
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#[doc = "DIR set register"]
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pub mod dirset;
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#[doc = "DIRCLR (rw) register accessor: an alias for `Reg<DIRCLR_SPEC>`"]
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pub type DIRCLR = crate::Reg<dirclr::DIRCLR_SPEC>;
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#[doc = "DIR clear register"]
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pub mod dirclr;
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#[doc = "LATCH (rw) register accessor: an alias for `Reg<LATCH_SPEC>`"]
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pub type LATCH = crate::Reg<latch::LATCH_SPEC>;
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#[doc = "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF\\[n\\].SENSE registers"]
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pub mod latch;
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#[doc = "DETECTMODE (rw) register accessor: an alias for `Reg<DETECTMODE_SPEC>`"]
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pub type DETECTMODE = crate::Reg<detectmode::DETECTMODE_SPEC>;
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#[doc = "Select between default DETECT signal behaviour and LDETECT mode"]
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pub mod detectmode;
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#[doc = "PIN_CNF (rw) register accessor: an alias for `Reg<PIN_CNF_SPEC>`"]
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pub type PIN_CNF = crate::Reg<pin_cnf::PIN_CNF_SPEC>;
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#[doc = "Description collection\\[n\\]: Configuration of GPIO pins"]
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pub mod pin_cnf;
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