swaits
a1b92356b3
First classic-ESP32 (non-S3) board in the firmware, and first SX127x radio. ESP32 + SX1276 + SSD1306 OLED + AXP192 PMIC, CP2102 USB-UART bridge. Pin map verified from MeshCore variants/lilygo_tbeam_SX1276. The AXP192 gates power to the LoRa chip and OLED. Its I²C bus is shared with the display, so the firmware builds I²C0 in blocking mode first for the PMIC init, then converts the same handle to async and hands it to the display task — avoids double-consuming the peripheral. Lora-phy's Sx127x support drives DIO0 as the sole IRQ (SX127x has no BUSY line); the chip runs from a crystal, tx_boost routes +20 dBm through PA_BOOST. The `esp-hal` / `esp-rtos` / `esp-backtrace` / `esp-println` deps have been restructured so the chip flavour (esp32 vs esp32s3) is selected at the per-board feature level instead of baked into the dep lines. This keeps the existing S3 boards building on esp32s3 while the new T-Beam feature selects classic esp32 via the same dependency set. LoRaBoard gains supported_sf_bitmap() / supported_bw_bitmap() methods (with SX126x defaults) so the T-Beam can report SF6–SF12 via GET_INFO — the SX1276 has no SF5. radio_chip_id() reports 0x0011 per donglora-protocol RadioChipId::Sx1276. freq_range_hz widens to the SX1276 datasheet span of 137 MHz–1020 MHz. New modules: - src/hal/esp32.rs — classic-ESP32 MCU primitives - src/board/esp32.rs — Sx127x radio + SSD1306 display pipe - src/board/lilygo_tbeam.rs — the board file - src/driver/axp.rs — AXP192 init added alongside AXP2101
66 lines
2.5 KiB
Markdown
66 lines
2.5 KiB
Markdown
# DongLoRa Firmware
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Embedded Rust firmware for DongLoRa boards. Exposes the LoRa radio over
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USB CDC-ACM using a COBS-framed binary protocol.
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## Building
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```sh
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just setup # one-time toolchain install
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just build heltec_v4 # build for a specific board
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just flash heltec_v4 # build + flash
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just check-all # compile-check all boards
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just clippy heltec_v4 # lint
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just test # host-side protocol unit tests
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```
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All commands are run from the `firmware/` directory.
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## Supported Boards
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| Board | Feature | MCU | Radio | USB | Target |
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|-------|---------|-----|-------|-----|--------|
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| Heltec V3 | `heltec_v3` | ESP32-S3 | SX1262 | Native CDC-ACM | xtensa-esp32s3-none-elf |
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| Heltec V3 (UART) | `heltec_v3_uart` | ESP32-S3 | SX1262 | CP2102 bridge | xtensa-esp32s3-none-elf |
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| Heltec V4 | `heltec_v4` | ESP32-S3 | SX1262 | Native CDC-ACM | xtensa-esp32s3-none-elf |
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| ELECROW ThinkNode-M2 | `elecrow_thinknode_m2` | ESP32-S3 | SX1262 | CP2102 bridge | xtensa-esp32s3-none-elf |
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| LilyGo T-Beam | `lilygo_tbeam` | ESP32 | SX1276 | CP2102 bridge | xtensa-esp32-none-elf |
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| LilyGo T-Beam S3 Supreme | `lilygo_tbeam_supreme` | ESP32-S3 | SX1262 | Native CDC-ACM | xtensa-esp32s3-none-elf |
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| RAK WisBlock 4631 | `rak_wisblock_4631` | nRF52840 | SX1262 | Native CDC-ACM | thumbv7em-none-eabihf |
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| Waveshare RP2040-LoRa | `waveshare_rp2040_lora` | RP2040 | SX1262 | Native CDC-ACM | thumbv6m-none-eabi |
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| Wio Tracker L1 | `wio_tracker_l1` | nRF52840 | SX1262 | Native CDC-ACM | thumbv7em-none-eabihf |
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### Heltec V3 USB Note
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The default `heltec_v3` build uses **native USB CDC-ACM**, which requires a
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hardware modification to your board. Stock Heltec V3 boards route USB through a
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CP2102 bridge chip to UART — the ESP32-S3's native USB pins (GPIO19/GPIO20) are
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routed to header pins but not connected to the USB connector.
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**To enable native USB on a Heltec V3:**
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1. Solder 0-ohm (or 22-ohm) resistors at pads **R29** (D+) and **R3** (D-)
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2. Disconnect the CP2102 from the USB connector's D+/D- lines (cut traces or
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remove the CP2102 bridge resistors)
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After this mod, the board appears as `/dev/ttyACM0` with the DongLoRa VID:PID
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(1209:5741), just like the V4 and nRF boards.
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**If you have a stock (unmodified) V3**, use `heltec_v3_uart` instead:
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```sh
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just build heltec_v3_uart
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just flash heltec_v3_uart
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```
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This builds firmware that communicates via the CP2102 bridge (appears as
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`/dev/ttyUSB0`).
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## Adding a Board
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See [src/board/PORTING.md](src/board/PORTING.md).
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## Protocol
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See [PROTOCOL.md](PROTOCOL.md) for the complete wire format specification.
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