swaits/donglora
Archived
1
0 Fork 0
Code Issues Actions Packages Projects Releases Wiki Activity

feat: add display UI with splash screen, dashboard, and RSSI sparkline

Browse Source 
Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
swaitsandClaude Opus 4.6 committed 2026-03-29 20:42:54 -06:00
1 parent 7064110293
commit 3102fc747a
17624 files changed
+4564928 -38
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

vendor/esp32s3/.cargo-checksum.json
Vendored
+1
View File
@@ -0,0 +1 @@
{"files":{".cargo_vcs_info.json":"31c156c9501d8fba3c002b25353432cfaa8cad2e2d81db5a7821a03768ce5181","Cargo.toml":"f6b8fc19a3193e59cd96990e8dfd200536c5fb1d3d08d17191bcd1b3e594b45c","Cargo.toml.orig":"eaa9cc05ce85209c16097edb16609dd26cd3556bacd152f5e992db1b55a7812f","README.md":"725212cc243f748819305cf3d952c37c18a03c6c3b1436ec22dae7135ea454d6","build.rs":"1bca6cb7989730c4d8f0bb57ed370c1f5c38c1585c1600fd739adb667ae69d5c","device.x":"03a554d09ca5ecbdef833130fa1e4d0d9d22a8e45833007f440b25608b17d151","src/aes.rs":"6236fb06d9bbc32d17e3479f11a409f03aff467299d11007aa578bff2b24decf","src/aes/aad_block_num.rs":"2628285dfe78b62f521411916181c20b0ff3f45d1cd5567539a0370161eb46dd","src/aes/block_mode.rs":"ecaf15486049043534d6de7ac08fb6c8434b44faf1e9a00f31afccabb2295b4a","src/aes/block_num.rs":"5727779142e9a66e928d6a65ac57f57c3d465a8654d2f3349c9c142bfebff4ad","src/aes/continue_.rs":"c847b61ac7a0b6f449d8bb2ac6af0e42a748659b5028adccf68528f156446dc0","src/aes/date.rs":"5fb48ef20608de3231fe0acaba5e63cf7138164d958c106f3732d643b595c0ae","src/aes/dma_enable.rs":"ab3e8006d23cd32ca42d0eb6bb2e589f05756909dcba9c5cddb1ae04dd3a958e","src/aes/dma_exit.rs":"89c25a29f06c2c70ce1cbd49d7bab88be36b813278ab1af7cb3346bdacf42561","src/aes/h_mem.rs":"d437bee50053ca126ffeb76a5e15c6ea7f7fef7d5886428c08adab47a1f01945","src/aes/inc_sel.rs":"8ba1a99ffa4daa735753908c1ff0601e7e6b59841d0e947fb1ce88052501c0a4","src/aes/int_clr.rs":"08e440fa361a11912d9a137820a6d7b97ca2a232209e4bd29efcccd3893ac7e8","src/aes/int_ena.rs":"35bd2c217dde00306fc2bf0c047e74f724dff3ac6dd100f6707b550f02449f6b","src/aes/iv_mem.rs":"9ea9120b22fa1dba2813975f441c3062f44d475904ec3d45924dafee36de2eb9","src/aes/j0_mem.rs":"9ae9a17196d23789c775c4033ddfdb42945094d78f1d63c15cc62cd3a7260b43","src/aes/key.rs":"373005dfeae6c7adbad633494aab740f8f108da0793b52ba97ffd57dad89791a","src/aes/mode.rs":"4d2d123612d746a28c56dff4b3dd830c3fa665dbd5347090bb31e79f71d918eb","src/aes/remainder_bit_num.rs":"8da402622286a853d90e700cf8d18577726a64ee49bda288cfda48e69757b885","src/aes/state.rs":"a95c1b5fd8b48e2a82ab0bfe436a87ab51fdc23e0e76fdf976c1f9ed81f4dd61","src/aes/t0_mem.rs":"fc97c362a7db48a1375e8bfdd1c42c58754ae59c2425b0a4e928ab9860258504","src/aes/text_in.rs":"6d8f591e61939678ed6b676cc2e011b1429a8f47731b63203bfdde8ee3b37cb3","src/aes/text_out.rs":"d60e5abdfcb3e0f7adba4a0317a8bf91d0efefd3d2a71bcf5dcf20bf13ddd333","src/aes/trigger.rs":"6409607105018f7e258026104feb291dda7b05ac0ce6a20da935ce3ffe1bce26","src/apb_ctrl.rs":"b62a7f50226e3ffb4a2d832e25d0a8eac22072ab74a3297ac491942c563f095d","src/apb_ctrl/clk_out_en.rs":"65e15157962c33b368beeebcd82926772bca34b99c091378aa8babd8596fe526","src/apb_ctrl/clkgate_force_on.rs":"23150bafa40ac3c7bc30a8d3397a915aa1b111aa157f39472d37843a994e1758","src/apb_ctrl/date.rs":"1b34b6d894d4a00678324a08b61adbee40e9a09e677452749eaf6af9628c3ead","src/apb_ctrl/ext_mem_pms_lock.rs":"05ba5e10d2d9de356507b1923363e116bac4a90addbc8ee877a01bd7a258a340","src/apb_ctrl/ext_mem_writeback_bypass.rs":"ca286b3b761d5d7fe002cd4e4ddee0f37b2197f009c933552d2d778660f58707","src/apb_ctrl/flash_ace0_addr.rs":"2a268c7dc55e41b40a8d080dfffdbd6dd2ef9464aebd60482919d4996beaa432","src/apb_ctrl/flash_ace0_attr.rs":"b3616939f51cabfd42b920850e22dcd1f99d8b01be91844721285e9034570e51","src/apb_ctrl/flash_ace0_size.rs":"93d3ad4eeff7ce5183dd6fb0fe00a8a525a0cbb715b13d1fb8fa7586070d6077","src/apb_ctrl/flash_ace1_addr.rs":"0060997aca9d0f24570a7ae7a03ac7d799f146bd3799b7f984a80337a5e398ae","src/apb_ctrl/flash_ace1_attr.rs":"81004d08331d5154345899f6a7ad4056fcb8f896754f434e00c5015fc12022fa","src/apb_ctrl/flash_ace1_size.rs":"f8ac52c924310fce8e5661102a12ab5426aebd3176c26f8510a9e662a2c98f7e","src/apb_ctrl/flash_ace2_addr.rs":"2429f821ba6cf8a7b2e5153df286dc27401955cb038d873a36ea49dbcc08b108","src/apb_ctrl/flash_ace2_attr.rs":"e1e96bec4927020d18fd41970d02a3d5484514366def217a8a7ba63d9cb569d0","src/apb_ctrl/flash_ace2_size.rs":"55ca07db985a9b4fe0db0397472ba1a46c19e9561301744d8f954a6f46a10321","src/apb_ctrl/flash_ace3_addr.rs":"b9ba9e313f5e04151f3a190b2ed6b1ab35c08f53c8e6e4a11fad6154f2b6867c","src/apb_ctrl/flash_ace3_attr.rs":"2b84f0a2fc073cb179d542641ba27629a71252b6dd9d44904e9dfbcce0abc1be","src/apb_ctrl/flash_ace3_size.rs":"1c9eba99e583364aa85fdded442e8230b67460f1cca185f3f2fc28d954da9928","src/apb_ctrl/front_end_mem_pd.rs":"a0d31a4c7963995bfcd467e7b3faf0c4ca934e125c1a20d22f0e94fe936b08ea","src/apb_ctrl/host_inf_sel.rs":"52f19b19cce2e4ee4ae9cc8aeab0d91f7fd04168bdd78d05f06330e9cd0fce0d","src/apb_ctrl/mem_power_down.rs":"c6831162bd81a4b49d434d351bdc8d21aa6253880bc200c3826c9f571c3ee557","src/apb_ctrl/mem_power_up.rs":"d07a167db50f4c7d7dd8324a463c65090c90261b4c8d6d9b01cbc813653f6f98","src/apb_ctrl/redcy_sig0.rs":"096dd6b2063cc1ad5a9966e19ec5c055abc9ae8a6b5d390c18da417462ae3e35","src/apb_ctrl/redcy_sig1.rs":"e6514cdd455a591a0c2bac1d91fa86a743b4ca8b21a17c2156ba2ac0c14a2ba7","src/apb_ctrl/retention_ctrl.rs":"8067489590ecbe611245ae0baffed394687ba790a9f1c0bb58ae935af106fff1","src/apb_ctrl/retention_ctrl1.rs":"7d3ba0ffb016fed42af70bc2e2a2ceb486134bLine truncated
vendor/esp32s3/.cargo_vcs_info.json
Vendored
+6
View File
@@ -0,0 +1,6 @@
{
"git": {
"sha1": "e0f26e63fe797faca6c8944e2e6efbed52e4b1bd"
},
"path_in_vcs": "esp32s3"
}
vendor/esp32s3/Cargo.toml
Vendored
+64
View File
@@ -0,0 +1,64 @@
# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
#
# When uploading crates to the registry Cargo will automatically
# "normalize" Cargo.toml files for maximal compatibility
# with all versions of Cargo and also rewrite `path` dependencies
# to registry (e.g., crates.io) dependencies.
#
# If you are reading this file be aware that the original Cargo.toml
# will likely look very different (and much more reasonable).
# See Cargo.toml.orig for the original contents.
[package]
edition = "2021"
rust-version = "1.76"
name = "esp32s3"
version = "0.29.0"
build = "build.rs"
include = [
"src/**",
"build.rs",
"device.x",
]
autobins = false
autoexamples = false
autotests = false
autobenches = false
description = "Peripheral access crate for the ESP32-S3"
readme = "README.md"
keywords = [
"embedded",
"esp32s3",
"no-std",
"wifi",
]
categories = [
"embedded",
"hardware-support",
"no-std",
]
license = "MIT OR Apache-2.0"
repository = "https://github.com/esp-rs/esp-pacs"
[lib]
name = "esp32s3"
path = "src/lib.rs"
test = false
bench = false
[dependencies.critical-section]
version = "1.1.3"
optional = true
[dependencies.defmt]
version = "0.3.8"
optional = true
[dependencies.vcell]
version = "0.1.3"
[features]
default = []
defmt = ["dep:defmt"]
impl-register-debug = []
rt = []
vendor/esp32s3/README.md
Vendored
+30
View File
@@ -0,0 +1,30 @@
# esp32s3
[![Crates.io](https://img.shields.io/crates/v/esp32s3?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp32s3)
[![docs.rs](https://img.shields.io/docsrs/esp32s3?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp32s3)
![Crates.io](https://img.shields.io/crates/l/esp32s3?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
A **P**eripheral **A**ccess **C**rate (**PAC**) for the **ESP32-S3** from Espressif. See the [svd2rust] repository for more information on how to use this crate.
If you find any problems with the included SVD file please open an issue in the [espressif/svd] repository so that the fixes can be applied upstream.
[svd2rust]: https://github.com/rust-embedded/svd2rust
[espressif/svd]: https://github.com/espressif/svd
## [Documentation](https://docs.rs/esp32s3)
## License
Licensed under either of:
- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
### Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
any additional terms or conditions.
vendor/esp32s3/build.rs
Vendored
+17
View File
@@ -0,0 +1,17 @@
#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
if env::var_os("CARGO_FEATURE_RT").is_some() {
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("device.x"))
.unwrap()
.write_all(include_bytes!("device.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=device.x");
}
println!("cargo:rerun-if-changed=build.rs");
}
vendor/esp32s3/device.x
Vendored
+95
View File
@@ -0,0 +1,95 @@
PROVIDE(WIFI_MAC = DefaultHandler);
PROVIDE(WIFI_NMI = DefaultHandler);
PROVIDE(WIFI_PWR = DefaultHandler);
PROVIDE(WIFI_BB = DefaultHandler);
PROVIDE(BT_MAC = DefaultHandler);
PROVIDE(BT_BB = DefaultHandler);
PROVIDE(BT_BB_NMI = DefaultHandler);
PROVIDE(RWBT = DefaultHandler);
PROVIDE(RWBLE = DefaultHandler);
PROVIDE(RWBT_NMI = DefaultHandler);
PROVIDE(RWBLE_NMI = DefaultHandler);
PROVIDE(I2C_MASTER = DefaultHandler);
PROVIDE(SLC0 = DefaultHandler);
PROVIDE(SLC1 = DefaultHandler);
PROVIDE(UHCI0 = DefaultHandler);
PROVIDE(UHCI1 = DefaultHandler);
PROVIDE(GPIO = DefaultHandler);
PROVIDE(GPIO_NMI = DefaultHandler);
PROVIDE(GPIO_INTR_2 = DefaultHandler);
PROVIDE(GPIO_NMI_2 = DefaultHandler);
PROVIDE(SPI1 = DefaultHandler);
PROVIDE(SPI2 = DefaultHandler);
PROVIDE(SPI3 = DefaultHandler);
PROVIDE(LCD_CAM = DefaultHandler);
PROVIDE(I2S0 = DefaultHandler);
PROVIDE(I2S1 = DefaultHandler);
PROVIDE(UART0 = DefaultHandler);
PROVIDE(UART1 = DefaultHandler);
PROVIDE(UART2 = DefaultHandler);
PROVIDE(SDIO_HOST = DefaultHandler);
PROVIDE(MCPWM0 = DefaultHandler);
PROVIDE(MCPWM1 = DefaultHandler);
PROVIDE(LEDC = DefaultHandler);
PROVIDE(EFUSE = DefaultHandler);
PROVIDE(TWAI0 = DefaultHandler);
PROVIDE(USB = DefaultHandler);
PROVIDE(RTC_CORE = DefaultHandler);
PROVIDE(RMT = DefaultHandler);
PROVIDE(PCNT = DefaultHandler);
PROVIDE(I2C_EXT0 = DefaultHandler);
PROVIDE(I2C_EXT1 = DefaultHandler);
PROVIDE(SPI2_DMA = DefaultHandler);
PROVIDE(SPI3_DMA = DefaultHandler);
PROVIDE(WDT = DefaultHandler);
PROVIDE(TIMER1 = DefaultHandler);
PROVIDE(TIMER2 = DefaultHandler);
PROVIDE(TG0_T0_LEVEL = DefaultHandler);
PROVIDE(TG0_T1_LEVEL = DefaultHandler);
PROVIDE(TG0_WDT_LEVEL = DefaultHandler);
PROVIDE(TG1_T0_LEVEL = DefaultHandler);
PROVIDE(TG1_T1_LEVEL = DefaultHandler);
PROVIDE(TG1_WDT_LEVEL = DefaultHandler);
PROVIDE(CACHE_IA = DefaultHandler);
PROVIDE(SYSTIMER_TARGET0 = DefaultHandler);
PROVIDE(SYSTIMER_TARGET1 = DefaultHandler);
PROVIDE(SYSTIMER_TARGET2 = DefaultHandler);
PROVIDE(SPI_MEM_REJECT_CACHE = DefaultHandler);
PROVIDE(DCACHE_PRELOAD0 = DefaultHandler);
PROVIDE(ICACHE_PRELOAD0 = DefaultHandler);
PROVIDE(DCACHE_SYNC0 = DefaultHandler);
PROVIDE(ICACHE_SYNC0 = DefaultHandler);
PROVIDE(APB_ADC = DefaultHandler);
PROVIDE(DMA_IN_CH0 = DefaultHandler);
PROVIDE(DMA_IN_CH1 = DefaultHandler);
PROVIDE(DMA_IN_CH2 = DefaultHandler);
PROVIDE(DMA_IN_CH3 = DefaultHandler);
PROVIDE(DMA_IN_CH4 = DefaultHandler);
PROVIDE(DMA_OUT_CH0 = DefaultHandler);
PROVIDE(DMA_OUT_CH1 = DefaultHandler);
PROVIDE(DMA_OUT_CH2 = DefaultHandler);
PROVIDE(DMA_OUT_CH3 = DefaultHandler);
PROVIDE(DMA_OUT_CH4 = DefaultHandler);
PROVIDE(RSA = DefaultHandler);
PROVIDE(SHA = DefaultHandler);
PROVIDE(FROM_CPU_INTR0 = DefaultHandler);
PROVIDE(FROM_CPU_INTR1 = DefaultHandler);
PROVIDE(FROM_CPU_INTR2 = DefaultHandler);
PROVIDE(FROM_CPU_INTR3 = DefaultHandler);
PROVIDE(ASSIST_DEBUG = DefaultHandler);
PROVIDE(DMA_APBPERI_PMS = DefaultHandler);
PROVIDE(CORE0_IRAM0_PMS = DefaultHandler);
PROVIDE(CORE0_DRAM0_PMS = DefaultHandler);
PROVIDE(CORE0_PIF_PMS = DefaultHandler);
PROVIDE(CORE0_PIF_PMS_SIZE = DefaultHandler);
PROVIDE(CORE1_IRAM0_PMS = DefaultHandler);
PROVIDE(CORE1_DRAM0_PMS = DefaultHandler);
PROVIDE(CORE1_PIF_PMS = DefaultHandler);
PROVIDE(CORE1_PIF_PMS_SIZE = DefaultHandler);
PROVIDE(BACKUP_PMS_VIOLATE = DefaultHandler);
PROVIDE(CACHE_CORE0_ACS = DefaultHandler);
PROVIDE(CACHE_CORE1_ACS = DefaultHandler);
PROVIDE(USB_DEVICE = DefaultHandler);
PROVIDE(PERI_BACKUP = DefaultHandler);
PROVIDE(DMA_EXTMEM_REJECT = DefaultHandler);
vendor/esp32s3/src/aes.rs
Vendored
+260
View File
@@ -0,0 +1,260 @@
#[repr(C)]
#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
#[doc = "Register block"]
pub struct RegisterBlock {
key: [KEY; 8],
text_in: [TEXT_IN; 4],
text_out: [TEXT_OUT; 4],
mode: MODE,
_reserved4: [u8; 0x04],
trigger: TRIGGER,
state: STATE,
iv_mem: [IV_MEM; 4],
h_mem: [H_MEM; 4],
j0_mem: [J0_MEM; 4],
t0_mem: [T0_MEM; 4],
dma_enable: DMA_ENABLE,
block_mode: BLOCK_MODE,
block_num: BLOCK_NUM,
inc_sel: INC_SEL,
aad_block_num: AAD_BLOCK_NUM,
remainder_bit_num: REMAINDER_BIT_NUM,
continue_: CONTINUE,
int_clr: INT_CLR,
int_ena: INT_ENA,
date: DATE,
dma_exit: DMA_EXIT,
}
impl RegisterBlock {
#[doc = "0x00..0x20 - AES key register %s"]
#[inline(always)]
pub const fn key(&self, n: usize) -> &KEY {
&self.key[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x00..0x20 - AES key register %s"]
#[inline(always)]
pub fn key_iter(&self) -> impl Iterator<Item = &KEY> {
self.key.iter()
}
#[doc = "0x20..0x30 - Source data register %s"]
#[inline(always)]
pub const fn text_in(&self, n: usize) -> &TEXT_IN {
&self.text_in[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x20..0x30 - Source data register %s"]
#[inline(always)]
pub fn text_in_iter(&self) -> impl Iterator<Item = &TEXT_IN> {
self.text_in.iter()
}
#[doc = "0x30..0x40 - Result data register %s"]
#[inline(always)]
pub const fn text_out(&self, n: usize) -> &TEXT_OUT {
&self.text_out[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x30..0x40 - Result data register %s"]
#[inline(always)]
pub fn text_out_iter(&self) -> impl Iterator<Item = &TEXT_OUT> {
self.text_out.iter()
}
#[doc = "0x40 - AES Mode register"]
#[inline(always)]
pub const fn mode(&self) -> &MODE {
&self.mode
}
#[doc = "0x48 - AES trigger register"]
#[inline(always)]
pub const fn trigger(&self) -> &TRIGGER {
&self.trigger
}
#[doc = "0x4c - AES state register"]
#[inline(always)]
pub const fn state(&self) -> &STATE {
&self.state
}
#[doc = "0x50..0x60 - The memory that stores initialization vector"]
#[inline(always)]
pub const fn iv_mem(&self, n: usize) -> &IV_MEM {
&self.iv_mem[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x50..0x60 - The memory that stores initialization vector"]
#[inline(always)]
pub fn iv_mem_iter(&self) -> impl Iterator<Item = &IV_MEM> {
self.iv_mem.iter()
}
#[doc = "0x60..0x70 - The memory that stores GCM hash subkey"]
#[inline(always)]
pub const fn h_mem(&self, n: usize) -> &H_MEM {
&self.h_mem[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x60..0x70 - The memory that stores GCM hash subkey"]
#[inline(always)]
pub fn h_mem_iter(&self) -> impl Iterator<Item = &H_MEM> {
self.h_mem.iter()
}
#[doc = "0x70..0x80 - The memory that stores J0"]
#[inline(always)]
pub const fn j0_mem(&self, n: usize) -> &J0_MEM {
&self.j0_mem[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x70..0x80 - The memory that stores J0"]
#[inline(always)]
pub fn j0_mem_iter(&self) -> impl Iterator<Item = &J0_MEM> {
self.j0_mem.iter()
}
#[doc = "0x80..0x90 - The memory that stores T0"]
#[inline(always)]
pub const fn t0_mem(&self, n: usize) -> &T0_MEM {
&self.t0_mem[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x80..0x90 - The memory that stores T0"]
#[inline(always)]
pub fn t0_mem_iter(&self) -> impl Iterator<Item = &T0_MEM> {
self.t0_mem.iter()
}
#[doc = "0x90 - AES accelerator working mode register"]
#[inline(always)]
pub const fn dma_enable(&self) -> &DMA_ENABLE {
&self.dma_enable
}
#[doc = "0x94 - AES cipher block mode register"]
#[inline(always)]
pub const fn block_mode(&self) -> &BLOCK_MODE {
&self.block_mode
}
#[doc = "0x98 - AES block number register"]
#[inline(always)]
pub const fn block_num(&self) -> &BLOCK_NUM {
&self.block_num
}
#[doc = "0x9c - Standard incrementing function configure register"]
#[inline(always)]
pub const fn inc_sel(&self) -> &INC_SEL {
&self.inc_sel
}
#[doc = "0xa0 - Additional Authential Data block number register"]
#[inline(always)]
pub const fn aad_block_num(&self) -> &AAD_BLOCK_NUM {
&self.aad_block_num
}
#[doc = "0xa4 - AES remainder bit number register"]
#[inline(always)]
pub const fn remainder_bit_num(&self) -> &REMAINDER_BIT_NUM {
&self.remainder_bit_num
}
#[doc = "0xa8 - AES continue register"]
#[inline(always)]
pub const fn continue_(&self) -> &CONTINUE {
&self.continue_
}
#[doc = "0xac - AES Interrupt clear register"]
#[inline(always)]
pub const fn int_clr(&self) -> &INT_CLR {
&self.int_clr
}
#[doc = "0xb0 - DMA-AES Interrupt enable register"]
#[inline(always)]
pub const fn int_ena(&self) -> &INT_ENA {
&self.int_ena
}
#[doc = "0xb4 - AES version control register"]
#[inline(always)]
pub const fn date(&self) -> &DATE {
&self.date
}
#[doc = "0xb8 - AES-DMA exit config"]
#[inline(always)]
pub const fn dma_exit(&self) -> &DMA_EXIT {
&self.dma_exit
}
}
#[doc = "KEY (rw) register accessor: AES key register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`key::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key`] module"]
pub type KEY = crate::Reg<key::KEY_SPEC>;
#[doc = "AES key register %s"]
pub mod key;
#[doc = "TEXT_IN (rw) register accessor: Source data register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`text_in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_in`] module"]
pub type TEXT_IN = crate::Reg<text_in::TEXT_IN_SPEC>;
#[doc = "Source data register %s"]
pub mod text_in;
#[doc = "TEXT_OUT (rw) register accessor: Result data register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`text_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_out`] module"]
pub type TEXT_OUT = crate::Reg<text_out::TEXT_OUT_SPEC>;
#[doc = "Result data register %s"]
pub mod text_out;
#[doc = "MODE (rw) register accessor: AES Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"]
pub type MODE = crate::Reg<mode::MODE_SPEC>;
#[doc = "AES Mode register"]
pub mod mode;
#[doc = "TRIGGER (w) register accessor: AES trigger register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigger::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigger`] module"]
pub type TRIGGER = crate::Reg<trigger::TRIGGER_SPEC>;
#[doc = "AES trigger register"]
pub mod trigger;
#[doc = "STATE (r) register accessor: AES state register\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
pub type STATE = crate::Reg<state::STATE_SPEC>;
#[doc = "AES state register"]
pub mod state;
#[doc = "IV_MEM (rw) register accessor: The memory that stores initialization vector\n\nYou can [`read`](crate::Reg::read) this register and get [`iv_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iv_mem`] module"]
pub type IV_MEM = crate::Reg<iv_mem::IV_MEM_SPEC>;
#[doc = "The memory that stores initialization vector"]
pub mod iv_mem;
#[doc = "H_MEM (rw) register accessor: The memory that stores GCM hash subkey\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h_mem`] module"]
pub type H_MEM = crate::Reg<h_mem::H_MEM_SPEC>;
#[doc = "The memory that stores GCM hash subkey"]
pub mod h_mem;
#[doc = "J0_MEM (rw) register accessor: The memory that stores J0\n\nYou can [`read`](crate::Reg::read) this register and get [`j0_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`j0_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@j0_mem`] module"]
pub type J0_MEM = crate::Reg<j0_mem::J0_MEM_SPEC>;
#[doc = "The memory that stores J0"]
pub mod j0_mem;
#[doc = "T0_MEM (rw) register accessor: The memory that stores T0\n\nYou can [`read`](crate::Reg::read) this register and get [`t0_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t0_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0_mem`] module"]
pub type T0_MEM = crate::Reg<t0_mem::T0_MEM_SPEC>;
#[doc = "The memory that stores T0"]
pub mod t0_mem;
#[doc = "DMA_ENABLE (rw) register accessor: AES accelerator working mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_enable`] module"]
pub type DMA_ENABLE = crate::Reg<dma_enable::DMA_ENABLE_SPEC>;
#[doc = "AES accelerator working mode register"]
pub mod dma_enable;
#[doc = "BLOCK_MODE (rw) register accessor: AES cipher block mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@block_mode`] module"]
pub type BLOCK_MODE = crate::Reg<block_mode::BLOCK_MODE_SPEC>;
#[doc = "AES cipher block mode register"]
pub mod block_mode;
#[doc = "BLOCK_NUM (rw) register accessor: AES block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@block_num`] module"]
pub type BLOCK_NUM = crate::Reg<block_num::BLOCK_NUM_SPEC>;
#[doc = "AES block number register"]
pub mod block_num;
#[doc = "INC_SEL (rw) register accessor: Standard incrementing function configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`inc_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inc_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inc_sel`] module"]
pub type INC_SEL = crate::Reg<inc_sel::INC_SEL_SPEC>;
#[doc = "Standard incrementing function configure register"]
pub mod inc_sel;
#[doc = "AAD_BLOCK_NUM (rw) register accessor: Additional Authential Data block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`aad_block_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aad_block_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aad_block_num`] module"]
pub type AAD_BLOCK_NUM = crate::Reg<aad_block_num::AAD_BLOCK_NUM_SPEC>;
#[doc = "Additional Authential Data block number register"]
pub mod aad_block_num;
#[doc = "REMAINDER_BIT_NUM (rw) register accessor: AES remainder bit number register\n\nYou can [`read`](crate::Reg::read) this register and get [`remainder_bit_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remainder_bit_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remainder_bit_num`] module"]
pub type REMAINDER_BIT_NUM = crate::Reg<remainder_bit_num::REMAINDER_BIT_NUM_SPEC>;
#[doc = "AES remainder bit number register"]
pub mod remainder_bit_num;
#[doc = "CONTINUE (w) register accessor: AES continue register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`continue_::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@continue_`] module"]
pub type CONTINUE = crate::Reg<continue_::CONTINUE_SPEC>;
#[doc = "AES continue register"]
pub mod continue_;
#[doc = "INT_CLR (w) register accessor: AES Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
#[doc = "AES Interrupt clear register"]
pub mod int_clr;
#[doc = "INT_ENA (rw) register accessor: DMA-AES Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
#[doc = "DMA-AES Interrupt enable register"]
pub mod int_ena;
#[doc = "DATE (rw) register accessor: AES version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
pub type DATE = crate::Reg<date::DATE_SPEC>;
#[doc = "AES version control register"]
pub mod date;
#[doc = "DMA_EXIT (w) register accessor: AES-DMA exit config\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_exit::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_exit`] module"]
pub type DMA_EXIT = crate::Reg<dma_exit::DMA_EXIT_SPEC>;
#[doc = "AES-DMA exit config"]
pub mod dma_exit;
vendor/esp32s3/src/aes/aad_block_num.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `AAD_BLOCK_NUM` reader"]
pub type R = crate::R<AAD_BLOCK_NUM_SPEC>;
#[doc = "Register `AAD_BLOCK_NUM` writer"]
pub type W = crate::W<AAD_BLOCK_NUM_SPEC>;
#[doc = "Field `AAD_BLOCK_NUM` reader - Those bits stores the number of AAD block."]
pub type AAD_BLOCK_NUM_R = crate::FieldReader<u32>;
#[doc = "Field `AAD_BLOCK_NUM` writer - Those bits stores the number of AAD block."]
pub type AAD_BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
#[inline(always)]
pub fn aad_block_num(&self) -> AAD_BLOCK_NUM_R {
AAD_BLOCK_NUM_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AAD_BLOCK_NUM")
.field("aad_block_num", &self.aad_block_num())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
#[inline(always)]
pub fn aad_block_num(&mut self) -> AAD_BLOCK_NUM_W<AAD_BLOCK_NUM_SPEC> {
AAD_BLOCK_NUM_W::new(self, 0)
}
}
#[doc = "Additional Authential Data block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`aad_block_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aad_block_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AAD_BLOCK_NUM_SPEC;
impl crate::RegisterSpec for AAD_BLOCK_NUM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`aad_block_num::R`](R) reader structure"]
impl crate::Readable for AAD_BLOCK_NUM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`aad_block_num::W`](W) writer structure"]
impl crate::Writable for AAD_BLOCK_NUM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AAD_BLOCK_NUM to value 0"]
impl crate::Resettable for AAD_BLOCK_NUM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/block_mode.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `BLOCK_MODE` reader"]
pub type R = crate::R<BLOCK_MODE_SPEC>;
#[doc = "Register `BLOCK_MODE` writer"]
pub type W = crate::W<BLOCK_MODE_SPEC>;
#[doc = "Field `BLOCK_MODE` reader - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
pub type BLOCK_MODE_R = crate::FieldReader;
#[doc = "Field `BLOCK_MODE` writer - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
pub type BLOCK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bits 0:2 - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
#[inline(always)]
pub fn block_mode(&self) -> BLOCK_MODE_R {
BLOCK_MODE_R::new((self.bits & 7) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BLOCK_MODE")
.field("block_mode", &self.block_mode())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
#[inline(always)]
pub fn block_mode(&mut self) -> BLOCK_MODE_W<BLOCK_MODE_SPEC> {
BLOCK_MODE_W::new(self, 0)
}
}
#[doc = "AES cipher block mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BLOCK_MODE_SPEC;
impl crate::RegisterSpec for BLOCK_MODE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`block_mode::R`](R) reader structure"]
impl crate::Readable for BLOCK_MODE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`block_mode::W`](W) writer structure"]
impl crate::Writable for BLOCK_MODE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BLOCK_MODE to value 0"]
impl crate::Resettable for BLOCK_MODE_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/block_num.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `BLOCK_NUM` reader"]
pub type R = crate::R<BLOCK_NUM_SPEC>;
#[doc = "Register `BLOCK_NUM` writer"]
pub type W = crate::W<BLOCK_NUM_SPEC>;
#[doc = "Field `BLOCK_NUM` reader - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
pub type BLOCK_NUM_R = crate::FieldReader<u32>;
#[doc = "Field `BLOCK_NUM` writer - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
pub type BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
#[inline(always)]
pub fn block_num(&self) -> BLOCK_NUM_R {
BLOCK_NUM_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BLOCK_NUM")
.field("block_num", &self.block_num())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
#[inline(always)]
pub fn block_num(&mut self) -> BLOCK_NUM_W<BLOCK_NUM_SPEC> {
BLOCK_NUM_W::new(self, 0)
}
}
#[doc = "AES block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BLOCK_NUM_SPEC;
impl crate::RegisterSpec for BLOCK_NUM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`block_num::R`](R) reader structure"]
impl crate::Readable for BLOCK_NUM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`block_num::W`](W) writer structure"]
impl crate::Writable for BLOCK_NUM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BLOCK_NUM to value 0"]
impl crate::Resettable for BLOCK_NUM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/continue_.rs
Vendored
+32
View File
@@ -0,0 +1,32 @@
#[doc = "Register `CONTINUE` writer"]
pub type W = crate::W<CONTINUE_SPEC>;
#[doc = "Field `CONTINUE` writer - Set this bit to 1 to continue GCM operation."]
pub type CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
#[doc = "Bit 0 - Set this bit to 1 to continue GCM operation."]
#[inline(always)]
pub fn continue_(&mut self) -> CONTINUE_W<CONTINUE_SPEC> {
CONTINUE_W::new(self, 0)
}
}
#[doc = "AES continue register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`continue_::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CONTINUE_SPEC;
impl crate::RegisterSpec for CONTINUE_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`continue_::W`](W) writer structure"]
impl crate::Writable for CONTINUE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONTINUE to value 0"]
impl crate::Resettable for CONTINUE_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/date.rs
Vendored
+45
View File
@@ -0,0 +1,45 @@
#[doc = "Register `DATE` reader"]
pub type R = crate::R<DATE_SPEC>;
#[doc = "Register `DATE` writer"]
pub type W = crate::W<DATE_SPEC>;
#[doc = "Field `DATE` reader - This bits stores the version information of AES."]
pub type DATE_R = crate::FieldReader<u32>;
#[doc = "Field `DATE` writer - This bits stores the version information of AES."]
pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bits 0:29 - This bits stores the version information of AES."]
#[inline(always)]
pub fn date(&self) -> DATE_R {
DATE_R::new(self.bits & 0x3fff_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DATE").field("date", &self.date()).finish()
}
}
impl W {
#[doc = "Bits 0:29 - This bits stores the version information of AES."]
#[inline(always)]
pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
DATE_W::new(self, 0)
}
}
#[doc = "AES version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATE_SPEC;
impl crate::RegisterSpec for DATE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`date::R`](R) reader structure"]
impl crate::Readable for DATE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
impl crate::Writable for DATE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DATE to value 0x2019_1210"]
impl crate::Resettable for DATE_SPEC {
const RESET_VALUE: u32 = 0x2019_1210;
}
vendor/esp32s3/src/aes/dma_enable.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `DMA_ENABLE` reader"]
pub type R = crate::R<DMA_ENABLE_SPEC>;
#[doc = "Register `DMA_ENABLE` writer"]
pub type W = crate::W<DMA_ENABLE_SPEC>;
#[doc = "Field `DMA_ENABLE` reader - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
pub type DMA_ENABLE_R = crate::BitReader;
#[doc = "Field `DMA_ENABLE` writer - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
pub type DMA_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
#[inline(always)]
pub fn dma_enable(&self) -> DMA_ENABLE_R {
DMA_ENABLE_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA_ENABLE")
.field("dma_enable", &self.dma_enable())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
#[inline(always)]
pub fn dma_enable(&mut self) -> DMA_ENABLE_W<DMA_ENABLE_SPEC> {
DMA_ENABLE_W::new(self, 0)
}
}
#[doc = "AES accelerator working mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMA_ENABLE_SPEC;
impl crate::RegisterSpec for DMA_ENABLE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma_enable::R`](R) reader structure"]
impl crate::Readable for DMA_ENABLE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`dma_enable::W`](W) writer structure"]
impl crate::Writable for DMA_ENABLE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DMA_ENABLE to value 0"]
impl crate::Resettable for DMA_ENABLE_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/dma_exit.rs
Vendored
+32
View File
@@ -0,0 +1,32 @@
#[doc = "Register `DMA_EXIT` writer"]
pub type W = crate::W<DMA_EXIT_SPEC>;
#[doc = "Field `DMA_EXIT` writer - Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation."]
pub type DMA_EXIT_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<DMA_EXIT_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
#[doc = "Bit 0 - Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation."]
#[inline(always)]
pub fn dma_exit(&mut self) -> DMA_EXIT_W<DMA_EXIT_SPEC> {
DMA_EXIT_W::new(self, 0)
}
}
#[doc = "AES-DMA exit config\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_exit::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMA_EXIT_SPEC;
impl crate::RegisterSpec for DMA_EXIT_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`dma_exit::W`](W) writer structure"]
impl crate::Writable for DMA_EXIT_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DMA_EXIT to value 0"]
impl crate::Resettable for DMA_EXIT_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/h_mem.rs
Vendored
+28
View File
@@ -0,0 +1,28 @@
#[doc = "Register `H_MEM[%s]` reader"]
pub type R = crate::R<H_MEM_SPEC>;
#[doc = "Register `H_MEM[%s]` writer"]
pub type W = crate::W<H_MEM_SPEC>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct H_MEM_SPEC;
impl crate::RegisterSpec for H_MEM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`h_mem::R`](R) reader structure"]
impl crate::Readable for H_MEM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`h_mem::W`](W) writer structure"]
impl crate::Writable for H_MEM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets H_MEM[%s] to value 0"]
impl crate::Resettable for H_MEM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/inc_sel.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `INC_SEL` reader"]
pub type R = crate::R<INC_SEL_SPEC>;
#[doc = "Register `INC_SEL` writer"]
pub type W = crate::W<INC_SEL_SPEC>;
#[doc = "Field `INC_SEL` reader - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
pub type INC_SEL_R = crate::BitReader;
#[doc = "Field `INC_SEL` writer - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
pub type INC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
#[inline(always)]
pub fn inc_sel(&self) -> INC_SEL_R {
INC_SEL_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INC_SEL")
.field("inc_sel", &self.inc_sel())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
#[inline(always)]
pub fn inc_sel(&mut self) -> INC_SEL_W<INC_SEL_SPEC> {
INC_SEL_W::new(self, 0)
}
}
#[doc = "Standard incrementing function configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`inc_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inc_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INC_SEL_SPEC;
impl crate::RegisterSpec for INC_SEL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`inc_sel::R`](R) reader structure"]
impl crate::Readable for INC_SEL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`inc_sel::W`](W) writer structure"]
impl crate::Writable for INC_SEL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INC_SEL to value 0"]
impl crate::Resettable for INC_SEL_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/int_clr.rs
Vendored
+32
View File
@@ -0,0 +1,32 @@
#[doc = "Register `INT_CLR` writer"]
pub type W = crate::W<INT_CLR_SPEC>;
#[doc = "Field `INT_CLR` writer - Set this bit to 1 to clear AES interrupt."]
pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
#[doc = "Bit 0 - Set this bit to 1 to clear AES interrupt."]
#[inline(always)]
pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
INT_CLR_W::new(self, 0)
}
}
#[doc = "AES Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_CLR_SPEC;
impl crate::RegisterSpec for INT_CLR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
impl crate::Writable for INT_CLR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_CLR to value 0"]
impl crate::Resettable for INT_CLR_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/int_ena.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `INT_ENA` reader"]
pub type R = crate::R<INT_ENA_SPEC>;
#[doc = "Register `INT_ENA` writer"]
pub type W = crate::W<INT_ENA_SPEC>;
#[doc = "Field `INT_ENA` reader - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
pub type INT_ENA_R = crate::BitReader;
#[doc = "Field `INT_ENA` writer - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
pub type INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
#[inline(always)]
pub fn int_ena(&self) -> INT_ENA_R {
INT_ENA_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_ENA")
.field("int_ena", &self.int_ena())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
#[inline(always)]
pub fn int_ena(&mut self) -> INT_ENA_W<INT_ENA_SPEC> {
INT_ENA_W::new(self, 0)
}
}
#[doc = "DMA-AES Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_ENA_SPEC;
impl crate::RegisterSpec for INT_ENA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
impl crate::Readable for INT_ENA_SPEC {}
#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
impl crate::Writable for INT_ENA_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_ENA to value 0"]
impl crate::Resettable for INT_ENA_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/iv_mem.rs
Vendored
+28
View File
@@ -0,0 +1,28 @@
#[doc = "Register `IV_MEM[%s]` reader"]
pub type R = crate::R<IV_MEM_SPEC>;
#[doc = "Register `IV_MEM[%s]` writer"]
pub type W = crate::W<IV_MEM_SPEC>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::Reg::read) this register and get [`iv_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IV_MEM_SPEC;
impl crate::RegisterSpec for IV_MEM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`iv_mem::R`](R) reader structure"]
impl crate::Readable for IV_MEM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`iv_mem::W`](W) writer structure"]
impl crate::Writable for IV_MEM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IV_MEM[%s] to value 0"]
impl crate::Resettable for IV_MEM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/j0_mem.rs
Vendored
+28
View File
@@ -0,0 +1,28 @@
#[doc = "Register `J0_MEM[%s]` reader"]
pub type R = crate::R<J0_MEM_SPEC>;
#[doc = "Register `J0_MEM[%s]` writer"]
pub type W = crate::W<J0_MEM_SPEC>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "The memory that stores J0\n\nYou can [`read`](crate::Reg::read) this register and get [`j0_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct J0_MEM_SPEC;
impl crate::RegisterSpec for J0_MEM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`j0_mem::R`](R) reader structure"]
impl crate::Readable for J0_MEM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`j0_mem::W`](W) writer structure"]
impl crate::Writable for J0_MEM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets J0_MEM[%s] to value 0"]
impl crate::Resettable for J0_MEM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/key.rs
Vendored
+45
View File
@@ -0,0 +1,45 @@
#[doc = "Register `KEY[%s]` reader"]
pub type R = crate::R<KEY_SPEC>;
#[doc = "Register `KEY[%s]` writer"]
pub type W = crate::W<KEY_SPEC>;
#[doc = "Field `KEY` reader - Stores AES keys."]
pub type KEY_R = crate::FieldReader<u32>;
#[doc = "Field `KEY` writer - Stores AES keys."]
pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
impl R {
#[doc = "Bits 0:31 - Stores AES keys."]
#[inline(always)]
pub fn key(&self) -> KEY_R {
KEY_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("KEY").field("key", &self.key()).finish()
}
}
impl W {
#[doc = "Bits 0:31 - Stores AES keys."]
#[inline(always)]
pub fn key(&mut self) -> KEY_W<KEY_SPEC> {
KEY_W::new(self, 0)
}
}
#[doc = "AES key register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`key::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct KEY_SPEC;
impl crate::RegisterSpec for KEY_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`key::R`](R) reader structure"]
impl crate::Readable for KEY_SPEC {}
#[doc = "`write(|w| ..)` method takes [`key::W`](W) writer structure"]
impl crate::Writable for KEY_SPEC {
type Safety = crate::Safe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets KEY[%s] to value 0"]
impl crate::Resettable for KEY_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/mode.rs
Vendored
+45
View File
@@ -0,0 +1,45 @@
#[doc = "Register `MODE` reader"]
pub type R = crate::R<MODE_SPEC>;
#[doc = "Register `MODE` writer"]
pub type W = crate::W<MODE_SPEC>;
#[doc = "Field `MODE` reader - Defines the key length and the encryption/decryption of the AES accelerator."]
pub type MODE_R = crate::FieldReader;
#[doc = "Field `MODE` writer - Defines the key length and the encryption/decryption of the AES accelerator."]
pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bits 0:2 - Defines the key length and the encryption/decryption of the AES accelerator."]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new((self.bits & 7) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MODE").field("mode", &self.mode()).finish()
}
}
impl W {
#[doc = "Bits 0:2 - Defines the key length and the encryption/decryption of the AES accelerator."]
#[inline(always)]
pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
MODE_W::new(self, 0)
}
}
#[doc = "AES Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MODE_SPEC;
impl crate::RegisterSpec for MODE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`mode::R`](R) reader structure"]
impl crate::Readable for MODE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
impl crate::Writable for MODE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MODE to value 0"]
impl crate::Resettable for MODE_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/remainder_bit_num.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `REMAINDER_BIT_NUM` reader"]
pub type R = crate::R<REMAINDER_BIT_NUM_SPEC>;
#[doc = "Register `REMAINDER_BIT_NUM` writer"]
pub type W = crate::W<REMAINDER_BIT_NUM_SPEC>;
#[doc = "Field `REMAINDER_BIT_NUM` reader - Those bits stores the number of remainder bit."]
pub type REMAINDER_BIT_NUM_R = crate::FieldReader;
#[doc = "Field `REMAINDER_BIT_NUM` writer - Those bits stores the number of remainder bit."]
pub type REMAINDER_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
#[inline(always)]
pub fn remainder_bit_num(&self) -> REMAINDER_BIT_NUM_R {
REMAINDER_BIT_NUM_R::new((self.bits & 0x7f) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("REMAINDER_BIT_NUM")
.field("remainder_bit_num", &self.remainder_bit_num())
.finish()
}
}
impl W {
#[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
#[inline(always)]
pub fn remainder_bit_num(&mut self) -> REMAINDER_BIT_NUM_W<REMAINDER_BIT_NUM_SPEC> {
REMAINDER_BIT_NUM_W::new(self, 0)
}
}
#[doc = "AES remainder bit number register\n\nYou can [`read`](crate::Reg::read) this register and get [`remainder_bit_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remainder_bit_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct REMAINDER_BIT_NUM_SPEC;
impl crate::RegisterSpec for REMAINDER_BIT_NUM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`remainder_bit_num::R`](R) reader structure"]
impl crate::Readable for REMAINDER_BIT_NUM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`remainder_bit_num::W`](W) writer structure"]
impl crate::Writable for REMAINDER_BIT_NUM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets REMAINDER_BIT_NUM to value 0"]
impl crate::Resettable for REMAINDER_BIT_NUM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/state.rs
Vendored
+30
View File
@@ -0,0 +1,30 @@
#[doc = "Register `STATE` reader"]
pub type R = crate::R<STATE_SPEC>;
#[doc = "Field `STATE` reader - Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done."]
pub type STATE_R = crate::FieldReader;
impl R {
#[doc = "Bits 0:1 - Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done."]
#[inline(always)]
pub fn state(&self) -> STATE_R {
STATE_R::new((self.bits & 3) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("STATE")
.field("state", &self.state())
.finish()
}
}
#[doc = "AES state register\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATE_SPEC;
impl crate::RegisterSpec for STATE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`state::R`](R) reader structure"]
impl crate::Readable for STATE_SPEC {}
#[doc = "`reset()` method sets STATE to value 0"]
impl crate::Resettable for STATE_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/t0_mem.rs
Vendored
+28
View File
@@ -0,0 +1,28 @@
#[doc = "Register `T0_MEM[%s]` reader"]
pub type R = crate::R<T0_MEM_SPEC>;
#[doc = "Register `T0_MEM[%s]` writer"]
pub type W = crate::W<T0_MEM_SPEC>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "The memory that stores T0\n\nYou can [`read`](crate::Reg::read) this register and get [`t0_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct T0_MEM_SPEC;
impl crate::RegisterSpec for T0_MEM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`t0_mem::R`](R) reader structure"]
impl crate::Readable for T0_MEM_SPEC {}
#[doc = "`write(|w| ..)` method takes [`t0_mem::W`](W) writer structure"]
impl crate::Writable for T0_MEM_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets T0_MEM[%s] to value 0"]
impl crate::Resettable for T0_MEM_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/text_in.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `TEXT_IN[%s]` reader"]
pub type R = crate::R<TEXT_IN_SPEC>;
#[doc = "Register `TEXT_IN[%s]` writer"]
pub type W = crate::W<TEXT_IN_SPEC>;
#[doc = "Field `TEXT_IN` reader - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
pub type TEXT_IN_R = crate::FieldReader<u32>;
#[doc = "Field `TEXT_IN` writer - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
pub type TEXT_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
impl R {
#[doc = "Bits 0:31 - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
#[inline(always)]
pub fn text_in(&self) -> TEXT_IN_R {
TEXT_IN_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TEXT_IN")
.field("text_in", &self.text_in())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
#[inline(always)]
pub fn text_in(&mut self) -> TEXT_IN_W<TEXT_IN_SPEC> {
TEXT_IN_W::new(self, 0)
}
}
#[doc = "Source data register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`text_in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TEXT_IN_SPEC;
impl crate::RegisterSpec for TEXT_IN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`text_in::R`](R) reader structure"]
impl crate::Readable for TEXT_IN_SPEC {}
#[doc = "`write(|w| ..)` method takes [`text_in::W`](W) writer structure"]
impl crate::Writable for TEXT_IN_SPEC {
type Safety = crate::Safe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TEXT_IN[%s] to value 0"]
impl crate::Resettable for TEXT_IN_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/text_out.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `TEXT_OUT[%s]` reader"]
pub type R = crate::R<TEXT_OUT_SPEC>;
#[doc = "Register `TEXT_OUT[%s]` writer"]
pub type W = crate::W<TEXT_OUT_SPEC>;
#[doc = "Field `TEXT_OUT` reader - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
pub type TEXT_OUT_R = crate::FieldReader<u32>;
#[doc = "Field `TEXT_OUT` writer - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
pub type TEXT_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
#[inline(always)]
pub fn text_out(&self) -> TEXT_OUT_R {
TEXT_OUT_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TEXT_OUT")
.field("text_out", &self.text_out())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
#[inline(always)]
pub fn text_out(&mut self) -> TEXT_OUT_W<TEXT_OUT_SPEC> {
TEXT_OUT_W::new(self, 0)
}
}
#[doc = "Result data register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`text_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TEXT_OUT_SPEC;
impl crate::RegisterSpec for TEXT_OUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`text_out::R`](R) reader structure"]
impl crate::Readable for TEXT_OUT_SPEC {}
#[doc = "`write(|w| ..)` method takes [`text_out::W`](W) writer structure"]
impl crate::Writable for TEXT_OUT_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TEXT_OUT[%s] to value 0"]
impl crate::Resettable for TEXT_OUT_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/aes/trigger.rs
Vendored
+32
View File
@@ -0,0 +1,32 @@
#[doc = "Register `TRIGGER` writer"]
pub type W = crate::W<TRIGGER_SPEC>;
#[doc = "Field `TRIGGER` writer - Set this bit to 1 to start AES calculation."]
pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
#[doc = "Bit 0 - Set this bit to 1 to start AES calculation."]
#[inline(always)]
pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
TRIGGER_W::new(self, 0)
}
}
#[doc = "AES trigger register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigger::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TRIGGER_SPEC;
impl crate::RegisterSpec for TRIGGER_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"]
impl crate::Writable for TRIGGER_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TRIGGER to value 0"]
impl crate::Resettable for TRIGGER_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl.rs
Vendored
+520
View File
@@ -0,0 +1,520 @@
#[repr(C)]
#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
#[doc = "Register block"]
pub struct RegisterBlock {
sysclk_conf: SYSCLK_CONF,
tick_conf: TICK_CONF,
clk_out_en: CLK_OUT_EN,
wifi_bb_cfg: WIFI_BB_CFG,
wifi_bb_cfg_2: WIFI_BB_CFG_2,
wifi_clk_en: WIFI_CLK_EN,
wifi_rst_en: WIFI_RST_EN,
host_inf_sel: HOST_INF_SEL,
ext_mem_pms_lock: EXT_MEM_PMS_LOCK,
ext_mem_writeback_bypass: EXT_MEM_WRITEBACK_BYPASS,
flash_ace0_attr: FLASH_ACE0_ATTR,
flash_ace1_attr: FLASH_ACE1_ATTR,
flash_ace2_attr: FLASH_ACE2_ATTR,
flash_ace3_attr: FLASH_ACE3_ATTR,
flash_ace0_addr: FLASH_ACE0_ADDR,
flash_ace1_addr: FLASH_ACE1_ADDR,
flash_ace2_addr: FLASH_ACE2_ADDR,
flash_ace3_addr: FLASH_ACE3_ADDR,
flash_ace0_size: FLASH_ACE0_SIZE,
flash_ace1_size: FLASH_ACE1_SIZE,
flash_ace2_size: FLASH_ACE2_SIZE,
flash_ace3_size: FLASH_ACE3_SIZE,
sram_ace0_attr: SRAM_ACE0_ATTR,
sram_ace1_attr: SRAM_ACE1_ATTR,
sram_ace2_attr: SRAM_ACE2_ATTR,
sram_ace3_attr: SRAM_ACE3_ATTR,
sram_ace0_addr: SRAM_ACE0_ADDR,
sram_ace1_addr: SRAM_ACE1_ADDR,
sram_ace2_addr: SRAM_ACE2_ADDR,
sram_ace3_addr: SRAM_ACE3_ADDR,
sram_ace0_size: SRAM_ACE0_SIZE,
sram_ace1_size: SRAM_ACE1_SIZE,
sram_ace2_size: SRAM_ACE2_SIZE,
sram_ace3_size: SRAM_ACE3_SIZE,
spi_mem_pms_ctrl: SPI_MEM_PMS_CTRL,
spi_mem_reject_addr: SPI_MEM_REJECT_ADDR,
sdio_ctrl: SDIO_CTRL,
redcy_sig0: REDCY_SIG0,
redcy_sig1: REDCY_SIG1,
front_end_mem_pd: FRONT_END_MEM_PD,
spi_mem_ecc_ctrl: SPI_MEM_ECC_CTRL,
_reserved41: [u8; 0x04],
clkgate_force_on: CLKGATE_FORCE_ON,
mem_power_down: MEM_POWER_DOWN,
mem_power_up: MEM_POWER_UP,
retention_ctrl: RETENTION_CTRL,
retention_ctrl1: RETENTION_CTRL1,
retention_ctrl2: RETENTION_CTRL2,
retention_ctrl3: RETENTION_CTRL3,
retention_ctrl4: RETENTION_CTRL4,
retention_ctrl5: RETENTION_CTRL5,
_reserved50: [u8; 0x0330],
date: DATE,
}
impl RegisterBlock {
#[doc = "0x00 - ******* Description ***********"]
#[inline(always)]
pub const fn sysclk_conf(&self) -> &SYSCLK_CONF {
&self.sysclk_conf
}
#[doc = "0x04 - ******* Description ***********"]
#[inline(always)]
pub const fn tick_conf(&self) -> &TICK_CONF {
&self.tick_conf
}
#[doc = "0x08 - ******* Description ***********"]
#[inline(always)]
pub const fn clk_out_en(&self) -> &CLK_OUT_EN {
&self.clk_out_en
}
#[doc = "0x0c - ******* Description ***********"]
#[inline(always)]
pub const fn wifi_bb_cfg(&self) -> &WIFI_BB_CFG {
&self.wifi_bb_cfg
}
#[doc = "0x10 - ******* Description ***********"]
#[inline(always)]
pub const fn wifi_bb_cfg_2(&self) -> &WIFI_BB_CFG_2 {
&self.wifi_bb_cfg_2
}
#[doc = "0x14 - ******* Description ***********"]
#[inline(always)]
pub const fn wifi_clk_en(&self) -> &WIFI_CLK_EN {
&self.wifi_clk_en
}
#[doc = "0x18 - ******* Description ***********"]
#[inline(always)]
pub const fn wifi_rst_en(&self) -> &WIFI_RST_EN {
&self.wifi_rst_en
}
#[doc = "0x1c - ******* Description ***********"]
#[inline(always)]
pub const fn host_inf_sel(&self) -> &HOST_INF_SEL {
&self.host_inf_sel
}
#[doc = "0x20 - ******* Description ***********"]
#[inline(always)]
pub const fn ext_mem_pms_lock(&self) -> &EXT_MEM_PMS_LOCK {
&self.ext_mem_pms_lock
}
#[doc = "0x24 - ******* Description ***********"]
#[inline(always)]
pub const fn ext_mem_writeback_bypass(&self) -> &EXT_MEM_WRITEBACK_BYPASS {
&self.ext_mem_writeback_bypass
}
#[doc = "0x28 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace0_attr(&self) -> &FLASH_ACE0_ATTR {
&self.flash_ace0_attr
}
#[doc = "0x2c - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace1_attr(&self) -> &FLASH_ACE1_ATTR {
&self.flash_ace1_attr
}
#[doc = "0x30 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace2_attr(&self) -> &FLASH_ACE2_ATTR {
&self.flash_ace2_attr
}
#[doc = "0x34 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace3_attr(&self) -> &FLASH_ACE3_ATTR {
&self.flash_ace3_attr
}
#[doc = "0x38 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace0_addr(&self) -> &FLASH_ACE0_ADDR {
&self.flash_ace0_addr
}
#[doc = "0x3c - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace1_addr(&self) -> &FLASH_ACE1_ADDR {
&self.flash_ace1_addr
}
#[doc = "0x40 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace2_addr(&self) -> &FLASH_ACE2_ADDR {
&self.flash_ace2_addr
}
#[doc = "0x44 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace3_addr(&self) -> &FLASH_ACE3_ADDR {
&self.flash_ace3_addr
}
#[doc = "0x48 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace0_size(&self) -> &FLASH_ACE0_SIZE {
&self.flash_ace0_size
}
#[doc = "0x4c - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace1_size(&self) -> &FLASH_ACE1_SIZE {
&self.flash_ace1_size
}
#[doc = "0x50 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace2_size(&self) -> &FLASH_ACE2_SIZE {
&self.flash_ace2_size
}
#[doc = "0x54 - ******* Description ***********"]
#[inline(always)]
pub const fn flash_ace3_size(&self) -> &FLASH_ACE3_SIZE {
&self.flash_ace3_size
}
#[doc = "0x58 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace0_attr(&self) -> &SRAM_ACE0_ATTR {
&self.sram_ace0_attr
}
#[doc = "0x5c - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace1_attr(&self) -> &SRAM_ACE1_ATTR {
&self.sram_ace1_attr
}
#[doc = "0x60 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace2_attr(&self) -> &SRAM_ACE2_ATTR {
&self.sram_ace2_attr
}
#[doc = "0x64 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace3_attr(&self) -> &SRAM_ACE3_ATTR {
&self.sram_ace3_attr
}
#[doc = "0x68 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace0_addr(&self) -> &SRAM_ACE0_ADDR {
&self.sram_ace0_addr
}
#[doc = "0x6c - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace1_addr(&self) -> &SRAM_ACE1_ADDR {
&self.sram_ace1_addr
}
#[doc = "0x70 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace2_addr(&self) -> &SRAM_ACE2_ADDR {
&self.sram_ace2_addr
}
#[doc = "0x74 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace3_addr(&self) -> &SRAM_ACE3_ADDR {
&self.sram_ace3_addr
}
#[doc = "0x78 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace0_size(&self) -> &SRAM_ACE0_SIZE {
&self.sram_ace0_size
}
#[doc = "0x7c - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace1_size(&self) -> &SRAM_ACE1_SIZE {
&self.sram_ace1_size
}
#[doc = "0x80 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace2_size(&self) -> &SRAM_ACE2_SIZE {
&self.sram_ace2_size
}
#[doc = "0x84 - ******* Description ***********"]
#[inline(always)]
pub const fn sram_ace3_size(&self) -> &SRAM_ACE3_SIZE {
&self.sram_ace3_size
}
#[doc = "0x88 - ******* Description ***********"]
#[inline(always)]
pub const fn spi_mem_pms_ctrl(&self) -> &SPI_MEM_PMS_CTRL {
&self.spi_mem_pms_ctrl
}
#[doc = "0x8c - ******* Description ***********"]
#[inline(always)]
pub const fn spi_mem_reject_addr(&self) -> &SPI_MEM_REJECT_ADDR {
&self.spi_mem_reject_addr
}
#[doc = "0x90 - ******* Description ***********"]
#[inline(always)]
pub const fn sdio_ctrl(&self) -> &SDIO_CTRL {
&self.sdio_ctrl
}
#[doc = "0x94 - ******* Description ***********"]
#[inline(always)]
pub const fn redcy_sig0(&self) -> &REDCY_SIG0 {
&self.redcy_sig0
}
#[doc = "0x98 - ******* Description ***********"]
#[inline(always)]
pub const fn redcy_sig1(&self) -> &REDCY_SIG1 {
&self.redcy_sig1
}
#[doc = "0x9c - ******* Description ***********"]
#[inline(always)]
pub const fn front_end_mem_pd(&self) -> &FRONT_END_MEM_PD {
&self.front_end_mem_pd
}
#[doc = "0xa0 - ******* Description ***********"]
#[inline(always)]
pub const fn spi_mem_ecc_ctrl(&self) -> &SPI_MEM_ECC_CTRL {
&self.spi_mem_ecc_ctrl
}
#[doc = "0xa8 - ******* Description ***********"]
#[inline(always)]
pub const fn clkgate_force_on(&self) -> &CLKGATE_FORCE_ON {
&self.clkgate_force_on
}
#[doc = "0xac - ******* Description ***********"]
#[inline(always)]
pub const fn mem_power_down(&self) -> &MEM_POWER_DOWN {
&self.mem_power_down
}
#[doc = "0xb0 - ******* Description ***********"]
#[inline(always)]
pub const fn mem_power_up(&self) -> &MEM_POWER_UP {
&self.mem_power_up
}
#[doc = "0xb4 - ******* Description ***********"]
#[inline(always)]
pub const fn retention_ctrl(&self) -> &RETENTION_CTRL {
&self.retention_ctrl
}
#[doc = "0xb8 - ******* Description ***********"]
#[inline(always)]
pub const fn retention_ctrl1(&self) -> &RETENTION_CTRL1 {
&self.retention_ctrl1
}
#[doc = "0xbc - ******* Description ***********"]
#[inline(always)]
pub const fn retention_ctrl2(&self) -> &RETENTION_CTRL2 {
&self.retention_ctrl2
}
#[doc = "0xc0 - ******* Description ***********"]
#[inline(always)]
pub const fn retention_ctrl3(&self) -> &RETENTION_CTRL3 {
&self.retention_ctrl3
}
#[doc = "0xc4 - ******* Description ***********"]
#[inline(always)]
pub const fn retention_ctrl4(&self) -> &RETENTION_CTRL4 {
&self.retention_ctrl4
}
#[doc = "0xc8 - ******* Description ***********"]
#[inline(always)]
pub const fn retention_ctrl5(&self) -> &RETENTION_CTRL5 {
&self.retention_ctrl5
}
#[doc = "0x3fc - ******* Description ***********"]
#[inline(always)]
pub const fn date(&self) -> &DATE {
&self.date
}
}
#[doc = "SYSCLK_CONF (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysclk_conf`] module"]
pub type SYSCLK_CONF = crate::Reg<sysclk_conf::SYSCLK_CONF_SPEC>;
#[doc = "******* Description ***********"]
pub mod sysclk_conf;
#[doc = "TICK_CONF (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`tick_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tick_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tick_conf`] module"]
pub type TICK_CONF = crate::Reg<tick_conf::TICK_CONF_SPEC>;
#[doc = "******* Description ***********"]
pub mod tick_conf;
#[doc = "CLK_OUT_EN (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_out_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_out_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_out_en`] module"]
pub type CLK_OUT_EN = crate::Reg<clk_out_en::CLK_OUT_EN_SPEC>;
#[doc = "******* Description ***********"]
pub mod clk_out_en;
#[doc = "WIFI_BB_CFG (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_bb_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_bb_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_bb_cfg`] module"]
pub type WIFI_BB_CFG = crate::Reg<wifi_bb_cfg::WIFI_BB_CFG_SPEC>;
#[doc = "******* Description ***********"]
pub mod wifi_bb_cfg;
#[doc = "WIFI_BB_CFG_2 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_bb_cfg_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_bb_cfg_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_bb_cfg_2`] module"]
pub type WIFI_BB_CFG_2 = crate::Reg<wifi_bb_cfg_2::WIFI_BB_CFG_2_SPEC>;
#[doc = "******* Description ***********"]
pub mod wifi_bb_cfg_2;
#[doc = "WIFI_CLK_EN (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_clk_en`] module"]
pub type WIFI_CLK_EN = crate::Reg<wifi_clk_en::WIFI_CLK_EN_SPEC>;
#[doc = "******* Description ***********"]
pub mod wifi_clk_en;
#[doc = "WIFI_RST_EN (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_rst_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_rst_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_rst_en`] module"]
pub type WIFI_RST_EN = crate::Reg<wifi_rst_en::WIFI_RST_EN_SPEC>;
#[doc = "******* Description ***********"]
pub mod wifi_rst_en;
#[doc = "HOST_INF_SEL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`host_inf_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`host_inf_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@host_inf_sel`] module"]
pub type HOST_INF_SEL = crate::Reg<host_inf_sel::HOST_INF_SEL_SPEC>;
#[doc = "******* Description ***********"]
pub mod host_inf_sel;
#[doc = "EXT_MEM_PMS_LOCK (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_mem_pms_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_mem_pms_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_mem_pms_lock`] module"]
pub type EXT_MEM_PMS_LOCK = crate::Reg<ext_mem_pms_lock::EXT_MEM_PMS_LOCK_SPEC>;
#[doc = "******* Description ***********"]
pub mod ext_mem_pms_lock;
#[doc = "EXT_MEM_WRITEBACK_BYPASS (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_mem_writeback_bypass::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_mem_writeback_bypass::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_mem_writeback_bypass`] module"]
pub type EXT_MEM_WRITEBACK_BYPASS =
crate::Reg<ext_mem_writeback_bypass::EXT_MEM_WRITEBACK_BYPASS_SPEC>;
#[doc = "******* Description ***********"]
pub mod ext_mem_writeback_bypass;
#[doc = "FLASH_ACE0_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace0_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace0_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace0_attr`] module"]
pub type FLASH_ACE0_ATTR = crate::Reg<flash_ace0_attr::FLASH_ACE0_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace0_attr;
#[doc = "FLASH_ACE1_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace1_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace1_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace1_attr`] module"]
pub type FLASH_ACE1_ATTR = crate::Reg<flash_ace1_attr::FLASH_ACE1_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace1_attr;
#[doc = "FLASH_ACE2_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace2_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace2_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace2_attr`] module"]
pub type FLASH_ACE2_ATTR = crate::Reg<flash_ace2_attr::FLASH_ACE2_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace2_attr;
#[doc = "FLASH_ACE3_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace3_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace3_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace3_attr`] module"]
pub type FLASH_ACE3_ATTR = crate::Reg<flash_ace3_attr::FLASH_ACE3_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace3_attr;
#[doc = "FLASH_ACE0_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace0_addr`] module"]
pub type FLASH_ACE0_ADDR = crate::Reg<flash_ace0_addr::FLASH_ACE0_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace0_addr;
#[doc = "FLASH_ACE1_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace1_addr`] module"]
pub type FLASH_ACE1_ADDR = crate::Reg<flash_ace1_addr::FLASH_ACE1_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace1_addr;
#[doc = "FLASH_ACE2_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace2_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace2_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace2_addr`] module"]
pub type FLASH_ACE2_ADDR = crate::Reg<flash_ace2_addr::FLASH_ACE2_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace2_addr;
#[doc = "FLASH_ACE3_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace3_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace3_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace3_addr`] module"]
pub type FLASH_ACE3_ADDR = crate::Reg<flash_ace3_addr::FLASH_ACE3_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace3_addr;
#[doc = "FLASH_ACE0_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace0_size`] module"]
pub type FLASH_ACE0_SIZE = crate::Reg<flash_ace0_size::FLASH_ACE0_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace0_size;
#[doc = "FLASH_ACE1_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace1_size`] module"]
pub type FLASH_ACE1_SIZE = crate::Reg<flash_ace1_size::FLASH_ACE1_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace1_size;
#[doc = "FLASH_ACE2_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace2_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace2_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace2_size`] module"]
pub type FLASH_ACE2_SIZE = crate::Reg<flash_ace2_size::FLASH_ACE2_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace2_size;
#[doc = "FLASH_ACE3_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace3_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace3_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ace3_size`] module"]
pub type FLASH_ACE3_SIZE = crate::Reg<flash_ace3_size::FLASH_ACE3_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod flash_ace3_size;
#[doc = "SRAM_ACE0_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace0_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace0_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace0_attr`] module"]
pub type SRAM_ACE0_ATTR = crate::Reg<sram_ace0_attr::SRAM_ACE0_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace0_attr;
#[doc = "SRAM_ACE1_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace1_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace1_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace1_attr`] module"]
pub type SRAM_ACE1_ATTR = crate::Reg<sram_ace1_attr::SRAM_ACE1_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace1_attr;
#[doc = "SRAM_ACE2_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace2_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace2_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace2_attr`] module"]
pub type SRAM_ACE2_ATTR = crate::Reg<sram_ace2_attr::SRAM_ACE2_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace2_attr;
#[doc = "SRAM_ACE3_ATTR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace3_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace3_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace3_attr`] module"]
pub type SRAM_ACE3_ATTR = crate::Reg<sram_ace3_attr::SRAM_ACE3_ATTR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace3_attr;
#[doc = "SRAM_ACE0_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace0_addr`] module"]
pub type SRAM_ACE0_ADDR = crate::Reg<sram_ace0_addr::SRAM_ACE0_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace0_addr;
#[doc = "SRAM_ACE1_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace1_addr`] module"]
pub type SRAM_ACE1_ADDR = crate::Reg<sram_ace1_addr::SRAM_ACE1_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace1_addr;
#[doc = "SRAM_ACE2_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace2_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace2_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace2_addr`] module"]
pub type SRAM_ACE2_ADDR = crate::Reg<sram_ace2_addr::SRAM_ACE2_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace2_addr;
#[doc = "SRAM_ACE3_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace3_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace3_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace3_addr`] module"]
pub type SRAM_ACE3_ADDR = crate::Reg<sram_ace3_addr::SRAM_ACE3_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace3_addr;
#[doc = "SRAM_ACE0_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace0_size`] module"]
pub type SRAM_ACE0_SIZE = crate::Reg<sram_ace0_size::SRAM_ACE0_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace0_size;
#[doc = "SRAM_ACE1_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace1_size`] module"]
pub type SRAM_ACE1_SIZE = crate::Reg<sram_ace1_size::SRAM_ACE1_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace1_size;
#[doc = "SRAM_ACE2_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace2_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace2_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace2_size`] module"]
pub type SRAM_ACE2_SIZE = crate::Reg<sram_ace2_size::SRAM_ACE2_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace2_size;
#[doc = "SRAM_ACE3_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace3_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace3_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ace3_size`] module"]
pub type SRAM_ACE3_SIZE = crate::Reg<sram_ace3_size::SRAM_ACE3_SIZE_SPEC>;
#[doc = "******* Description ***********"]
pub mod sram_ace3_size;
#[doc = "SPI_MEM_PMS_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_mem_pms_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_mem_pms_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_pms_ctrl`] module"]
pub type SPI_MEM_PMS_CTRL = crate::Reg<spi_mem_pms_ctrl::SPI_MEM_PMS_CTRL_SPEC>;
#[doc = "******* Description ***********"]
pub mod spi_mem_pms_ctrl;
#[doc = "SPI_MEM_REJECT_ADDR (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_mem_reject_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_reject_addr`] module"]
pub type SPI_MEM_REJECT_ADDR = crate::Reg<spi_mem_reject_addr::SPI_MEM_REJECT_ADDR_SPEC>;
#[doc = "******* Description ***********"]
pub mod spi_mem_reject_addr;
#[doc = "SDIO_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sdio_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdio_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdio_ctrl`] module"]
pub type SDIO_CTRL = crate::Reg<sdio_ctrl::SDIO_CTRL_SPEC>;
#[doc = "******* Description ***********"]
pub mod sdio_ctrl;
#[doc = "REDCY_SIG0 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`redcy_sig0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`redcy_sig0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redcy_sig0`] module"]
pub type REDCY_SIG0 = crate::Reg<redcy_sig0::REDCY_SIG0_SPEC>;
#[doc = "******* Description ***********"]
pub mod redcy_sig0;
#[doc = "REDCY_SIG1 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`redcy_sig1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`redcy_sig1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redcy_sig1`] module"]
pub type REDCY_SIG1 = crate::Reg<redcy_sig1::REDCY_SIG1_SPEC>;
#[doc = "******* Description ***********"]
pub mod redcy_sig1;
#[doc = "FRONT_END_MEM_PD (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`front_end_mem_pd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`front_end_mem_pd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@front_end_mem_pd`] module"]
pub type FRONT_END_MEM_PD = crate::Reg<front_end_mem_pd::FRONT_END_MEM_PD_SPEC>;
#[doc = "******* Description ***********"]
pub mod front_end_mem_pd;
#[doc = "SPI_MEM_ECC_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_mem_ecc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_mem_ecc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ecc_ctrl`] module"]
pub type SPI_MEM_ECC_CTRL = crate::Reg<spi_mem_ecc_ctrl::SPI_MEM_ECC_CTRL_SPEC>;
#[doc = "******* Description ***********"]
pub mod spi_mem_ecc_ctrl;
#[doc = "CLKGATE_FORCE_ON (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clkgate_force_on::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkgate_force_on::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkgate_force_on`] module"]
pub type CLKGATE_FORCE_ON = crate::Reg<clkgate_force_on::CLKGATE_FORCE_ON_SPEC>;
#[doc = "******* Description ***********"]
pub mod clkgate_force_on;
#[doc = "MEM_POWER_DOWN (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_power_down::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_power_down::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_power_down`] module"]
pub type MEM_POWER_DOWN = crate::Reg<mem_power_down::MEM_POWER_DOWN_SPEC>;
#[doc = "******* Description ***********"]
pub mod mem_power_down;
#[doc = "MEM_POWER_UP (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_power_up::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_power_up::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_power_up`] module"]
pub type MEM_POWER_UP = crate::Reg<mem_power_up::MEM_POWER_UP_SPEC>;
#[doc = "******* Description ***********"]
pub mod mem_power_up;
#[doc = "RETENTION_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retention_ctrl`] module"]
pub type RETENTION_CTRL = crate::Reg<retention_ctrl::RETENTION_CTRL_SPEC>;
#[doc = "******* Description ***********"]
pub mod retention_ctrl;
#[doc = "RETENTION_CTRL1 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retention_ctrl1`] module"]
pub type RETENTION_CTRL1 = crate::Reg<retention_ctrl1::RETENTION_CTRL1_SPEC>;
#[doc = "******* Description ***********"]
pub mod retention_ctrl1;
#[doc = "RETENTION_CTRL2 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retention_ctrl2`] module"]
pub type RETENTION_CTRL2 = crate::Reg<retention_ctrl2::RETENTION_CTRL2_SPEC>;
#[doc = "******* Description ***********"]
pub mod retention_ctrl2;
#[doc = "RETENTION_CTRL3 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retention_ctrl3`] module"]
pub type RETENTION_CTRL3 = crate::Reg<retention_ctrl3::RETENTION_CTRL3_SPEC>;
#[doc = "******* Description ***********"]
pub mod retention_ctrl3;
#[doc = "RETENTION_CTRL4 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retention_ctrl4`] module"]
pub type RETENTION_CTRL4 = crate::Reg<retention_ctrl4::RETENTION_CTRL4_SPEC>;
#[doc = "******* Description ***********"]
pub mod retention_ctrl4;
#[doc = "RETENTION_CTRL5 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@retention_ctrl5`] module"]
pub type RETENTION_CTRL5 = crate::Reg<retention_ctrl5::RETENTION_CTRL5_SPEC>;
#[doc = "******* Description ***********"]
pub mod retention_ctrl5;
#[doc = "DATE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
pub type DATE = crate::Reg<date::DATE_SPEC>;
#[doc = "******* Description ***********"]
pub mod date;
vendor/esp32s3/src/apb_ctrl/clk_out_en.rs
Vendored
+197
View File
@@ -0,0 +1,197 @@
#[doc = "Register `CLK_OUT_EN` reader"]
pub type R = crate::R<CLK_OUT_EN_SPEC>;
#[doc = "Register `CLK_OUT_EN` writer"]
pub type W = crate::W<CLK_OUT_EN_SPEC>;
#[doc = "Field `CLK20_OEN` reader - ******* Description ***********"]
pub type CLK20_OEN_R = crate::BitReader;
#[doc = "Field `CLK20_OEN` writer - ******* Description ***********"]
pub type CLK20_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK22_OEN` reader - ******* Description ***********"]
pub type CLK22_OEN_R = crate::BitReader;
#[doc = "Field `CLK22_OEN` writer - ******* Description ***********"]
pub type CLK22_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK44_OEN` reader - ******* Description ***********"]
pub type CLK44_OEN_R = crate::BitReader;
#[doc = "Field `CLK44_OEN` writer - ******* Description ***********"]
pub type CLK44_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_BB_OEN` reader - ******* Description ***********"]
pub type CLK_BB_OEN_R = crate::BitReader;
#[doc = "Field `CLK_BB_OEN` writer - ******* Description ***********"]
pub type CLK_BB_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK80_OEN` reader - ******* Description ***********"]
pub type CLK80_OEN_R = crate::BitReader;
#[doc = "Field `CLK80_OEN` writer - ******* Description ***********"]
pub type CLK80_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK160_OEN` reader - ******* Description ***********"]
pub type CLK160_OEN_R = crate::BitReader;
#[doc = "Field `CLK160_OEN` writer - ******* Description ***********"]
pub type CLK160_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_320M_OEN` reader - ******* Description ***********"]
pub type CLK_320M_OEN_R = crate::BitReader;
#[doc = "Field `CLK_320M_OEN` writer - ******* Description ***********"]
pub type CLK_320M_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_ADC_INF_OEN` reader - ******* Description ***********"]
pub type CLK_ADC_INF_OEN_R = crate::BitReader;
#[doc = "Field `CLK_ADC_INF_OEN` writer - ******* Description ***********"]
pub type CLK_ADC_INF_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_DAC_CPU_OEN` reader - ******* Description ***********"]
pub type CLK_DAC_CPU_OEN_R = crate::BitReader;
#[doc = "Field `CLK_DAC_CPU_OEN` writer - ******* Description ***********"]
pub type CLK_DAC_CPU_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK40X_BB_OEN` reader - ******* Description ***********"]
pub type CLK40X_BB_OEN_R = crate::BitReader;
#[doc = "Field `CLK40X_BB_OEN` writer - ******* Description ***********"]
pub type CLK40X_BB_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_XTAL_OEN` reader - ******* Description ***********"]
pub type CLK_XTAL_OEN_R = crate::BitReader;
#[doc = "Field `CLK_XTAL_OEN` writer - ******* Description ***********"]
pub type CLK_XTAL_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn clk20_oen(&self) -> CLK20_OEN_R {
CLK20_OEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ******* Description ***********"]
#[inline(always)]
pub fn clk22_oen(&self) -> CLK22_OEN_R {
CLK22_OEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ******* Description ***********"]
#[inline(always)]
pub fn clk44_oen(&self) -> CLK44_OEN_R {
CLK44_OEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ******* Description ***********"]
#[inline(always)]
pub fn clk_bb_oen(&self) -> CLK_BB_OEN_R {
CLK_BB_OEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ******* Description ***********"]
#[inline(always)]
pub fn clk80_oen(&self) -> CLK80_OEN_R {
CLK80_OEN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ******* Description ***********"]
#[inline(always)]
pub fn clk160_oen(&self) -> CLK160_OEN_R {
CLK160_OEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ******* Description ***********"]
#[inline(always)]
pub fn clk_320m_oen(&self) -> CLK_320M_OEN_R {
CLK_320M_OEN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ******* Description ***********"]
#[inline(always)]
pub fn clk_adc_inf_oen(&self) -> CLK_ADC_INF_OEN_R {
CLK_ADC_INF_OEN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - ******* Description ***********"]
#[inline(always)]
pub fn clk_dac_cpu_oen(&self) -> CLK_DAC_CPU_OEN_R {
CLK_DAC_CPU_OEN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ******* Description ***********"]
#[inline(always)]
pub fn clk40x_bb_oen(&self) -> CLK40X_BB_OEN_R {
CLK40X_BB_OEN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - ******* Description ***********"]
#[inline(always)]
pub fn clk_xtal_oen(&self) -> CLK_XTAL_OEN_R {
CLK_XTAL_OEN_R::new(((self.bits >> 10) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CLK_OUT_EN")
.field("clk20_oen", &self.clk20_oen())
.field("clk22_oen", &self.clk22_oen())
.field("clk44_oen", &self.clk44_oen())
.field("clk_bb_oen", &self.clk_bb_oen())
.field("clk80_oen", &self.clk80_oen())
.field("clk160_oen", &self.clk160_oen())
.field("clk_320m_oen", &self.clk_320m_oen())
.field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
.field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
.field("clk40x_bb_oen", &self.clk40x_bb_oen())
.field("clk_xtal_oen", &self.clk_xtal_oen())
.finish()
}
}
impl W {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn clk20_oen(&mut self) -> CLK20_OEN_W<CLK_OUT_EN_SPEC> {
CLK20_OEN_W::new(self, 0)
}
#[doc = "Bit 1 - ******* Description ***********"]
#[inline(always)]
pub fn clk22_oen(&mut self) -> CLK22_OEN_W<CLK_OUT_EN_SPEC> {
CLK22_OEN_W::new(self, 1)
}
#[doc = "Bit 2 - ******* Description ***********"]
#[inline(always)]
pub fn clk44_oen(&mut self) -> CLK44_OEN_W<CLK_OUT_EN_SPEC> {
CLK44_OEN_W::new(self, 2)
}
#[doc = "Bit 3 - ******* Description ***********"]
#[inline(always)]
pub fn clk_bb_oen(&mut self) -> CLK_BB_OEN_W<CLK_OUT_EN_SPEC> {
CLK_BB_OEN_W::new(self, 3)
}
#[doc = "Bit 4 - ******* Description ***********"]
#[inline(always)]
pub fn clk80_oen(&mut self) -> CLK80_OEN_W<CLK_OUT_EN_SPEC> {
CLK80_OEN_W::new(self, 4)
}
#[doc = "Bit 5 - ******* Description ***********"]
#[inline(always)]
pub fn clk160_oen(&mut self) -> CLK160_OEN_W<CLK_OUT_EN_SPEC> {
CLK160_OEN_W::new(self, 5)
}
#[doc = "Bit 6 - ******* Description ***********"]
#[inline(always)]
pub fn clk_320m_oen(&mut self) -> CLK_320M_OEN_W<CLK_OUT_EN_SPEC> {
CLK_320M_OEN_W::new(self, 6)
}
#[doc = "Bit 7 - ******* Description ***********"]
#[inline(always)]
pub fn clk_adc_inf_oen(&mut self) -> CLK_ADC_INF_OEN_W<CLK_OUT_EN_SPEC> {
CLK_ADC_INF_OEN_W::new(self, 7)
}
#[doc = "Bit 8 - ******* Description ***********"]
#[inline(always)]
pub fn clk_dac_cpu_oen(&mut self) -> CLK_DAC_CPU_OEN_W<CLK_OUT_EN_SPEC> {
CLK_DAC_CPU_OEN_W::new(self, 8)
}
#[doc = "Bit 9 - ******* Description ***********"]
#[inline(always)]
pub fn clk40x_bb_oen(&mut self) -> CLK40X_BB_OEN_W<CLK_OUT_EN_SPEC> {
CLK40X_BB_OEN_W::new(self, 9)
}
#[doc = "Bit 10 - ******* Description ***********"]
#[inline(always)]
pub fn clk_xtal_oen(&mut self) -> CLK_XTAL_OEN_W<CLK_OUT_EN_SPEC> {
CLK_XTAL_OEN_W::new(self, 10)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_out_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_out_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLK_OUT_EN_SPEC;
impl crate::RegisterSpec for CLK_OUT_EN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`clk_out_en::R`](R) reader structure"]
impl crate::Readable for CLK_OUT_EN_SPEC {}
#[doc = "`write(|w| ..)` method takes [`clk_out_en::W`](W) writer structure"]
impl crate::Writable for CLK_OUT_EN_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CLK_OUT_EN to value 0x07ff"]
impl crate::Resettable for CLK_OUT_EN_SPEC {
const RESET_VALUE: u32 = 0x07ff;
}
vendor/esp32s3/src/apb_ctrl/clkgate_force_on.rs
Vendored
+62
View File
@@ -0,0 +1,62 @@
#[doc = "Register `CLKGATE_FORCE_ON` reader"]
pub type R = crate::R<CLKGATE_FORCE_ON_SPEC>;
#[doc = "Register `CLKGATE_FORCE_ON` writer"]
pub type W = crate::W<CLKGATE_FORCE_ON_SPEC>;
#[doc = "Field `ROM_CLKGATE_FORCE_ON` reader - ******* Description ***********"]
pub type ROM_CLKGATE_FORCE_ON_R = crate::FieldReader;
#[doc = "Field `ROM_CLKGATE_FORCE_ON` writer - ******* Description ***********"]
pub type ROM_CLKGATE_FORCE_ON_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SRAM_CLKGATE_FORCE_ON` reader - ******* Description ***********"]
pub type SRAM_CLKGATE_FORCE_ON_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_CLKGATE_FORCE_ON` writer - ******* Description ***********"]
pub type SRAM_CLKGATE_FORCE_ON_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - ******* Description ***********"]
#[inline(always)]
pub fn rom_clkgate_force_on(&self) -> ROM_CLKGATE_FORCE_ON_R {
ROM_CLKGATE_FORCE_ON_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:13 - ******* Description ***********"]
#[inline(always)]
pub fn sram_clkgate_force_on(&self) -> SRAM_CLKGATE_FORCE_ON_R {
SRAM_CLKGATE_FORCE_ON_R::new(((self.bits >> 3) & 0x07ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CLKGATE_FORCE_ON")
.field("rom_clkgate_force_on", &self.rom_clkgate_force_on())
.field("sram_clkgate_force_on", &self.sram_clkgate_force_on())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - ******* Description ***********"]
#[inline(always)]
pub fn rom_clkgate_force_on(&mut self) -> ROM_CLKGATE_FORCE_ON_W<CLKGATE_FORCE_ON_SPEC> {
ROM_CLKGATE_FORCE_ON_W::new(self, 0)
}
#[doc = "Bits 3:13 - ******* Description ***********"]
#[inline(always)]
pub fn sram_clkgate_force_on(&mut self) -> SRAM_CLKGATE_FORCE_ON_W<CLKGATE_FORCE_ON_SPEC> {
SRAM_CLKGATE_FORCE_ON_W::new(self, 3)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clkgate_force_on::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkgate_force_on::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKGATE_FORCE_ON_SPEC;
impl crate::RegisterSpec for CLKGATE_FORCE_ON_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`clkgate_force_on::R`](R) reader structure"]
impl crate::Readable for CLKGATE_FORCE_ON_SPEC {}
#[doc = "`write(|w| ..)` method takes [`clkgate_force_on::W`](W) writer structure"]
impl crate::Writable for CLKGATE_FORCE_ON_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CLKGATE_FORCE_ON to value 0x3fff"]
impl crate::Resettable for CLKGATE_FORCE_ON_SPEC {
const RESET_VALUE: u32 = 0x3fff;
}
vendor/esp32s3/src/apb_ctrl/date.rs
Vendored
+45
View File
@@ -0,0 +1,45 @@
#[doc = "Register `DATE` reader"]
pub type R = crate::R<DATE_SPEC>;
#[doc = "Register `DATE` writer"]
pub type W = crate::W<DATE_SPEC>;
#[doc = "Field `DATE` reader - Version control"]
pub type DATE_R = crate::FieldReader<u32>;
#[doc = "Field `DATE` writer - Version control"]
pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Version control"]
#[inline(always)]
pub fn date(&self) -> DATE_R {
DATE_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DATE").field("date", &self.date()).finish()
}
}
impl W {
#[doc = "Bits 0:31 - Version control"]
#[inline(always)]
pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
DATE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATE_SPEC;
impl crate::RegisterSpec for DATE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`date::R`](R) reader structure"]
impl crate::Readable for DATE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
impl crate::Writable for DATE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DATE to value 0x0210_1150"]
impl crate::Resettable for DATE_SPEC {
const RESET_VALUE: u32 = 0x0210_1150;
}
vendor/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `EXT_MEM_PMS_LOCK` reader"]
pub type R = crate::R<EXT_MEM_PMS_LOCK_SPEC>;
#[doc = "Register `EXT_MEM_PMS_LOCK` writer"]
pub type W = crate::W<EXT_MEM_PMS_LOCK_SPEC>;
#[doc = "Field `EXT_MEM_PMS_LOCK` reader - ******* Description ***********"]
pub type EXT_MEM_PMS_LOCK_R = crate::BitReader;
#[doc = "Field `EXT_MEM_PMS_LOCK` writer - ******* Description ***********"]
pub type EXT_MEM_PMS_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn ext_mem_pms_lock(&self) -> EXT_MEM_PMS_LOCK_R {
EXT_MEM_PMS_LOCK_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXT_MEM_PMS_LOCK")
.field("ext_mem_pms_lock", &self.ext_mem_pms_lock())
.finish()
}
}
impl W {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn ext_mem_pms_lock(&mut self) -> EXT_MEM_PMS_LOCK_W<EXT_MEM_PMS_LOCK_SPEC> {
EXT_MEM_PMS_LOCK_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_mem_pms_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_mem_pms_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXT_MEM_PMS_LOCK_SPEC;
impl crate::RegisterSpec for EXT_MEM_PMS_LOCK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_mem_pms_lock::R`](R) reader structure"]
impl crate::Readable for EXT_MEM_PMS_LOCK_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ext_mem_pms_lock::W`](W) writer structure"]
impl crate::Writable for EXT_MEM_PMS_LOCK_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXT_MEM_PMS_LOCK to value 0"]
impl crate::Resettable for EXT_MEM_PMS_LOCK_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `EXT_MEM_WRITEBACK_BYPASS` reader"]
pub type R = crate::R<EXT_MEM_WRITEBACK_BYPASS_SPEC>;
#[doc = "Register `EXT_MEM_WRITEBACK_BYPASS` writer"]
pub type W = crate::W<EXT_MEM_WRITEBACK_BYPASS_SPEC>;
#[doc = "Field `WRITEBACK_BYPASS` reader - Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute."]
pub type WRITEBACK_BYPASS_R = crate::BitReader;
#[doc = "Field `WRITEBACK_BYPASS` writer - Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute."]
pub type WRITEBACK_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute."]
#[inline(always)]
pub fn writeback_bypass(&self) -> WRITEBACK_BYPASS_R {
WRITEBACK_BYPASS_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXT_MEM_WRITEBACK_BYPASS")
.field("writeback_bypass", &self.writeback_bypass())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute."]
#[inline(always)]
pub fn writeback_bypass(&mut self) -> WRITEBACK_BYPASS_W<EXT_MEM_WRITEBACK_BYPASS_SPEC> {
WRITEBACK_BYPASS_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_mem_writeback_bypass::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_mem_writeback_bypass::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXT_MEM_WRITEBACK_BYPASS_SPEC;
impl crate::RegisterSpec for EXT_MEM_WRITEBACK_BYPASS_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_mem_writeback_bypass::R`](R) reader structure"]
impl crate::Readable for EXT_MEM_WRITEBACK_BYPASS_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ext_mem_writeback_bypass::W`](W) writer structure"]
impl crate::Writable for EXT_MEM_WRITEBACK_BYPASS_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXT_MEM_WRITEBACK_BYPASS to value 0"]
impl crate::Resettable for EXT_MEM_WRITEBACK_BYPASS_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE0_ADDR` reader"]
pub type R = crate::R<FLASH_ACE0_ADDR_SPEC>;
#[doc = "Register `FLASH_ACE0_ADDR` writer"]
pub type W = crate::W<FLASH_ACE0_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE0_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<FLASH_ACE0_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE0_ADDR_SPEC;
impl crate::RegisterSpec for FLASH_ACE0_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace0_addr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE0_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace0_addr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE0_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE0_ADDR to value 0"]
impl crate::Resettable for FLASH_ACE0_ADDR_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE0_ATTR` reader"]
pub type R = crate::R<FLASH_ACE0_ATTR_SPEC>;
#[doc = "Register `FLASH_ACE0_ATTR` writer"]
pub type W = crate::W<FLASH_ACE0_ATTR_SPEC>;
#[doc = "Field `FLASH_ACE0_ATTR` reader - ******* Description ***********"]
pub type FLASH_ACE0_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE0_ATTR` writer - ******* Description ***********"]
pub type FLASH_ACE0_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace0_attr(&self) -> FLASH_ACE0_ATTR_R {
FLASH_ACE0_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE0_ATTR")
.field("flash_ace0_attr", &self.flash_ace0_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace0_attr(&mut self) -> FLASH_ACE0_ATTR_W<FLASH_ACE0_ATTR_SPEC> {
FLASH_ACE0_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace0_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace0_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE0_ATTR_SPEC;
impl crate::RegisterSpec for FLASH_ACE0_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace0_attr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE0_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace0_attr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE0_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE0_ATTR to value 0xff"]
impl crate::Resettable for FLASH_ACE0_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/flash_ace0_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE0_SIZE` reader"]
pub type R = crate::R<FLASH_ACE0_SIZE_SPEC>;
#[doc = "Register `FLASH_ACE0_SIZE` writer"]
pub type W = crate::W<FLASH_ACE0_SIZE_SPEC>;
#[doc = "Field `FLASH_ACE0_SIZE` reader - ******* Description ***********"]
pub type FLASH_ACE0_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE0_SIZE` writer - ******* Description ***********"]
pub type FLASH_ACE0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace0_size(&self) -> FLASH_ACE0_SIZE_R {
FLASH_ACE0_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE0_SIZE")
.field("flash_ace0_size", &self.flash_ace0_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace0_size(&mut self) -> FLASH_ACE0_SIZE_W<FLASH_ACE0_SIZE_SPEC> {
FLASH_ACE0_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace0_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace0_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE0_SIZE_SPEC;
impl crate::RegisterSpec for FLASH_ACE0_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace0_size::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE0_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace0_size::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE0_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE0_SIZE to value 0x1000"]
impl crate::Resettable for FLASH_ACE0_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE1_ADDR` reader"]
pub type R = crate::R<FLASH_ACE1_ADDR_SPEC>;
#[doc = "Register `FLASH_ACE1_ADDR` writer"]
pub type W = crate::W<FLASH_ACE1_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE1_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<FLASH_ACE1_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE1_ADDR_SPEC;
impl crate::RegisterSpec for FLASH_ACE1_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace1_addr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE1_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace1_addr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE1_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE1_ADDR to value 0x1000_0000"]
impl crate::Resettable for FLASH_ACE1_ADDR_SPEC {
const RESET_VALUE: u32 = 0x1000_0000;
}
vendor/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE1_ATTR` reader"]
pub type R = crate::R<FLASH_ACE1_ATTR_SPEC>;
#[doc = "Register `FLASH_ACE1_ATTR` writer"]
pub type W = crate::W<FLASH_ACE1_ATTR_SPEC>;
#[doc = "Field `FLASH_ACE1_ATTR` reader - ******* Description ***********"]
pub type FLASH_ACE1_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE1_ATTR` writer - ******* Description ***********"]
pub type FLASH_ACE1_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace1_attr(&self) -> FLASH_ACE1_ATTR_R {
FLASH_ACE1_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE1_ATTR")
.field("flash_ace1_attr", &self.flash_ace1_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace1_attr(&mut self) -> FLASH_ACE1_ATTR_W<FLASH_ACE1_ATTR_SPEC> {
FLASH_ACE1_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace1_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace1_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE1_ATTR_SPEC;
impl crate::RegisterSpec for FLASH_ACE1_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace1_attr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE1_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace1_attr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE1_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE1_ATTR to value 0xff"]
impl crate::Resettable for FLASH_ACE1_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/flash_ace1_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE1_SIZE` reader"]
pub type R = crate::R<FLASH_ACE1_SIZE_SPEC>;
#[doc = "Register `FLASH_ACE1_SIZE` writer"]
pub type W = crate::W<FLASH_ACE1_SIZE_SPEC>;
#[doc = "Field `FLASH_ACE1_SIZE` reader - ******* Description ***********"]
pub type FLASH_ACE1_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE1_SIZE` writer - ******* Description ***********"]
pub type FLASH_ACE1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace1_size(&self) -> FLASH_ACE1_SIZE_R {
FLASH_ACE1_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE1_SIZE")
.field("flash_ace1_size", &self.flash_ace1_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace1_size(&mut self) -> FLASH_ACE1_SIZE_W<FLASH_ACE1_SIZE_SPEC> {
FLASH_ACE1_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace1_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace1_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE1_SIZE_SPEC;
impl crate::RegisterSpec for FLASH_ACE1_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace1_size::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE1_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace1_size::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE1_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE1_SIZE to value 0x1000"]
impl crate::Resettable for FLASH_ACE1_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE2_ADDR` reader"]
pub type R = crate::R<FLASH_ACE2_ADDR_SPEC>;
#[doc = "Register `FLASH_ACE2_ADDR` writer"]
pub type W = crate::W<FLASH_ACE2_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE2_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<FLASH_ACE2_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace2_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace2_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE2_ADDR_SPEC;
impl crate::RegisterSpec for FLASH_ACE2_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace2_addr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE2_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace2_addr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE2_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE2_ADDR to value 0x2000_0000"]
impl crate::Resettable for FLASH_ACE2_ADDR_SPEC {
const RESET_VALUE: u32 = 0x2000_0000;
}
vendor/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE2_ATTR` reader"]
pub type R = crate::R<FLASH_ACE2_ATTR_SPEC>;
#[doc = "Register `FLASH_ACE2_ATTR` writer"]
pub type W = crate::W<FLASH_ACE2_ATTR_SPEC>;
#[doc = "Field `FLASH_ACE2_ATTR` reader - ******* Description ***********"]
pub type FLASH_ACE2_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE2_ATTR` writer - ******* Description ***********"]
pub type FLASH_ACE2_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace2_attr(&self) -> FLASH_ACE2_ATTR_R {
FLASH_ACE2_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE2_ATTR")
.field("flash_ace2_attr", &self.flash_ace2_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace2_attr(&mut self) -> FLASH_ACE2_ATTR_W<FLASH_ACE2_ATTR_SPEC> {
FLASH_ACE2_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace2_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace2_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE2_ATTR_SPEC;
impl crate::RegisterSpec for FLASH_ACE2_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace2_attr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE2_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace2_attr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE2_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE2_ATTR to value 0xff"]
impl crate::Resettable for FLASH_ACE2_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/flash_ace2_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE2_SIZE` reader"]
pub type R = crate::R<FLASH_ACE2_SIZE_SPEC>;
#[doc = "Register `FLASH_ACE2_SIZE` writer"]
pub type W = crate::W<FLASH_ACE2_SIZE_SPEC>;
#[doc = "Field `FLASH_ACE2_SIZE` reader - ******* Description ***********"]
pub type FLASH_ACE2_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE2_SIZE` writer - ******* Description ***********"]
pub type FLASH_ACE2_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace2_size(&self) -> FLASH_ACE2_SIZE_R {
FLASH_ACE2_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE2_SIZE")
.field("flash_ace2_size", &self.flash_ace2_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace2_size(&mut self) -> FLASH_ACE2_SIZE_W<FLASH_ACE2_SIZE_SPEC> {
FLASH_ACE2_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace2_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace2_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE2_SIZE_SPEC;
impl crate::RegisterSpec for FLASH_ACE2_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace2_size::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE2_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace2_size::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE2_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE2_SIZE to value 0x1000"]
impl crate::Resettable for FLASH_ACE2_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE3_ADDR` reader"]
pub type R = crate::R<FLASH_ACE3_ADDR_SPEC>;
#[doc = "Register `FLASH_ACE3_ADDR` writer"]
pub type W = crate::W<FLASH_ACE3_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE3_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<FLASH_ACE3_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace3_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace3_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE3_ADDR_SPEC;
impl crate::RegisterSpec for FLASH_ACE3_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace3_addr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE3_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace3_addr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE3_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE3_ADDR to value 0x3000_0000"]
impl crate::Resettable for FLASH_ACE3_ADDR_SPEC {
const RESET_VALUE: u32 = 0x3000_0000;
}
vendor/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE3_ATTR` reader"]
pub type R = crate::R<FLASH_ACE3_ATTR_SPEC>;
#[doc = "Register `FLASH_ACE3_ATTR` writer"]
pub type W = crate::W<FLASH_ACE3_ATTR_SPEC>;
#[doc = "Field `FLASH_ACE3_ATTR` reader - ******* Description ***********"]
pub type FLASH_ACE3_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE3_ATTR` writer - ******* Description ***********"]
pub type FLASH_ACE3_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace3_attr(&self) -> FLASH_ACE3_ATTR_R {
FLASH_ACE3_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE3_ATTR")
.field("flash_ace3_attr", &self.flash_ace3_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace3_attr(&mut self) -> FLASH_ACE3_ATTR_W<FLASH_ACE3_ATTR_SPEC> {
FLASH_ACE3_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace3_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace3_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE3_ATTR_SPEC;
impl crate::RegisterSpec for FLASH_ACE3_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace3_attr::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE3_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace3_attr::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE3_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE3_ATTR to value 0xff"]
impl crate::Resettable for FLASH_ACE3_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/flash_ace3_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `FLASH_ACE3_SIZE` reader"]
pub type R = crate::R<FLASH_ACE3_SIZE_SPEC>;
#[doc = "Register `FLASH_ACE3_SIZE` writer"]
pub type W = crate::W<FLASH_ACE3_SIZE_SPEC>;
#[doc = "Field `FLASH_ACE3_SIZE` reader - ******* Description ***********"]
pub type FLASH_ACE3_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `FLASH_ACE3_SIZE` writer - ******* Description ***********"]
pub type FLASH_ACE3_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace3_size(&self) -> FLASH_ACE3_SIZE_R {
FLASH_ACE3_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ACE3_SIZE")
.field("flash_ace3_size", &self.flash_ace3_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn flash_ace3_size(&mut self) -> FLASH_ACE3_SIZE_W<FLASH_ACE3_SIZE_SPEC> {
FLASH_ACE3_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ace3_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ace3_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASH_ACE3_SIZE_SPEC;
impl crate::RegisterSpec for FLASH_ACE3_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ace3_size::R`](R) reader structure"]
impl crate::Readable for FLASH_ACE3_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`flash_ace3_size::W`](W) writer structure"]
impl crate::Writable for FLASH_ACE3_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASH_ACE3_SIZE to value 0x1000"]
impl crate::Resettable for FLASH_ACE3_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
Vendored
+152
View File
@@ -0,0 +1,152 @@
#[doc = "Register `FRONT_END_MEM_PD` reader"]
pub type R = crate::R<FRONT_END_MEM_PD_SPEC>;
#[doc = "Register `FRONT_END_MEM_PD` writer"]
pub type W = crate::W<FRONT_END_MEM_PD_SPEC>;
#[doc = "Field `AGC_MEM_FORCE_PU` reader - ******* Description ***********"]
pub type AGC_MEM_FORCE_PU_R = crate::BitReader;
#[doc = "Field `AGC_MEM_FORCE_PU` writer - ******* Description ***********"]
pub type AGC_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AGC_MEM_FORCE_PD` reader - ******* Description ***********"]
pub type AGC_MEM_FORCE_PD_R = crate::BitReader;
#[doc = "Field `AGC_MEM_FORCE_PD` writer - ******* Description ***********"]
pub type AGC_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PBUS_MEM_FORCE_PU` reader - ******* Description ***********"]
pub type PBUS_MEM_FORCE_PU_R = crate::BitReader;
#[doc = "Field `PBUS_MEM_FORCE_PU` writer - ******* Description ***********"]
pub type PBUS_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PBUS_MEM_FORCE_PD` reader - ******* Description ***********"]
pub type PBUS_MEM_FORCE_PD_R = crate::BitReader;
#[doc = "Field `PBUS_MEM_FORCE_PD` writer - ******* Description ***********"]
pub type PBUS_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DC_MEM_FORCE_PU` reader - ******* Description ***********"]
pub type DC_MEM_FORCE_PU_R = crate::BitReader;
#[doc = "Field `DC_MEM_FORCE_PU` writer - ******* Description ***********"]
pub type DC_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DC_MEM_FORCE_PD` reader - ******* Description ***********"]
pub type DC_MEM_FORCE_PD_R = crate::BitReader;
#[doc = "Field `DC_MEM_FORCE_PD` writer - ******* Description ***********"]
pub type DC_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FREQ_MEM_FORCE_PU` reader - ******* Description ***********"]
pub type FREQ_MEM_FORCE_PU_R = crate::BitReader;
#[doc = "Field `FREQ_MEM_FORCE_PU` writer - ******* Description ***********"]
pub type FREQ_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FREQ_MEM_FORCE_PD` reader - ******* Description ***********"]
pub type FREQ_MEM_FORCE_PD_R = crate::BitReader;
#[doc = "Field `FREQ_MEM_FORCE_PD` writer - ******* Description ***********"]
pub type FREQ_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn agc_mem_force_pu(&self) -> AGC_MEM_FORCE_PU_R {
AGC_MEM_FORCE_PU_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ******* Description ***********"]
#[inline(always)]
pub fn agc_mem_force_pd(&self) -> AGC_MEM_FORCE_PD_R {
AGC_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ******* Description ***********"]
#[inline(always)]
pub fn pbus_mem_force_pu(&self) -> PBUS_MEM_FORCE_PU_R {
PBUS_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ******* Description ***********"]
#[inline(always)]
pub fn pbus_mem_force_pd(&self) -> PBUS_MEM_FORCE_PD_R {
PBUS_MEM_FORCE_PD_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ******* Description ***********"]
#[inline(always)]
pub fn dc_mem_force_pu(&self) -> DC_MEM_FORCE_PU_R {
DC_MEM_FORCE_PU_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ******* Description ***********"]
#[inline(always)]
pub fn dc_mem_force_pd(&self) -> DC_MEM_FORCE_PD_R {
DC_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ******* Description ***********"]
#[inline(always)]
pub fn freq_mem_force_pu(&self) -> FREQ_MEM_FORCE_PU_R {
FREQ_MEM_FORCE_PU_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ******* Description ***********"]
#[inline(always)]
pub fn freq_mem_force_pd(&self) -> FREQ_MEM_FORCE_PD_R {
FREQ_MEM_FORCE_PD_R::new(((self.bits >> 7) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FRONT_END_MEM_PD")
.field("agc_mem_force_pu", &self.agc_mem_force_pu())
.field("agc_mem_force_pd", &self.agc_mem_force_pd())
.field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
.field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
.field("dc_mem_force_pu", &self.dc_mem_force_pu())
.field("dc_mem_force_pd", &self.dc_mem_force_pd())
.field("freq_mem_force_pu", &self.freq_mem_force_pu())
.field("freq_mem_force_pd", &self.freq_mem_force_pd())
.finish()
}
}
impl W {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn agc_mem_force_pu(&mut self) -> AGC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
AGC_MEM_FORCE_PU_W::new(self, 0)
}
#[doc = "Bit 1 - ******* Description ***********"]
#[inline(always)]
pub fn agc_mem_force_pd(&mut self) -> AGC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
AGC_MEM_FORCE_PD_W::new(self, 1)
}
#[doc = "Bit 2 - ******* Description ***********"]
#[inline(always)]
pub fn pbus_mem_force_pu(&mut self) -> PBUS_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
PBUS_MEM_FORCE_PU_W::new(self, 2)
}
#[doc = "Bit 3 - ******* Description ***********"]
#[inline(always)]
pub fn pbus_mem_force_pd(&mut self) -> PBUS_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
PBUS_MEM_FORCE_PD_W::new(self, 3)
}
#[doc = "Bit 4 - ******* Description ***********"]
#[inline(always)]
pub fn dc_mem_force_pu(&mut self) -> DC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
DC_MEM_FORCE_PU_W::new(self, 4)
}
#[doc = "Bit 5 - ******* Description ***********"]
#[inline(always)]
pub fn dc_mem_force_pd(&mut self) -> DC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
DC_MEM_FORCE_PD_W::new(self, 5)
}
#[doc = "Bit 6 - ******* Description ***********"]
#[inline(always)]
pub fn freq_mem_force_pu(&mut self) -> FREQ_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
FREQ_MEM_FORCE_PU_W::new(self, 6)
}
#[doc = "Bit 7 - ******* Description ***********"]
#[inline(always)]
pub fn freq_mem_force_pd(&mut self) -> FREQ_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
FREQ_MEM_FORCE_PD_W::new(self, 7)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`front_end_mem_pd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`front_end_mem_pd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FRONT_END_MEM_PD_SPEC;
impl crate::RegisterSpec for FRONT_END_MEM_PD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`front_end_mem_pd::R`](R) reader structure"]
impl crate::Readable for FRONT_END_MEM_PD_SPEC {}
#[doc = "`write(|w| ..)` method takes [`front_end_mem_pd::W`](W) writer structure"]
impl crate::Writable for FRONT_END_MEM_PD_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FRONT_END_MEM_PD to value 0x55"]
impl crate::Resettable for FRONT_END_MEM_PD_SPEC {
const RESET_VALUE: u32 = 0x55;
}
vendor/esp32s3/src/apb_ctrl/host_inf_sel.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `HOST_INF_SEL` reader"]
pub type R = crate::R<HOST_INF_SEL_SPEC>;
#[doc = "Register `HOST_INF_SEL` writer"]
pub type W = crate::W<HOST_INF_SEL_SPEC>;
#[doc = "Field `PERI_IO_SWAP` reader - ******* Description ***********"]
pub type PERI_IO_SWAP_R = crate::FieldReader;
#[doc = "Field `PERI_IO_SWAP` writer - ******* Description ***********"]
pub type PERI_IO_SWAP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - ******* Description ***********"]
#[inline(always)]
pub fn peri_io_swap(&self) -> PERI_IO_SWAP_R {
PERI_IO_SWAP_R::new((self.bits & 0xff) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HOST_INF_SEL")
.field("peri_io_swap", &self.peri_io_swap())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - ******* Description ***********"]
#[inline(always)]
pub fn peri_io_swap(&mut self) -> PERI_IO_SWAP_W<HOST_INF_SEL_SPEC> {
PERI_IO_SWAP_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`host_inf_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`host_inf_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HOST_INF_SEL_SPEC;
impl crate::RegisterSpec for HOST_INF_SEL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`host_inf_sel::R`](R) reader structure"]
impl crate::Readable for HOST_INF_SEL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`host_inf_sel::W`](W) writer structure"]
impl crate::Writable for HOST_INF_SEL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HOST_INF_SEL to value 0"]
impl crate::Resettable for HOST_INF_SEL_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/mem_power_down.rs
Vendored
+62
View File
@@ -0,0 +1,62 @@
#[doc = "Register `MEM_POWER_DOWN` reader"]
pub type R = crate::R<MEM_POWER_DOWN_SPEC>;
#[doc = "Register `MEM_POWER_DOWN` writer"]
pub type W = crate::W<MEM_POWER_DOWN_SPEC>;
#[doc = "Field `ROM_POWER_DOWN` reader - ******* Description ***********"]
pub type ROM_POWER_DOWN_R = crate::FieldReader;
#[doc = "Field `ROM_POWER_DOWN` writer - ******* Description ***********"]
pub type ROM_POWER_DOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SRAM_POWER_DOWN` reader - ******* Description ***********"]
pub type SRAM_POWER_DOWN_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_POWER_DOWN` writer - ******* Description ***********"]
pub type SRAM_POWER_DOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - ******* Description ***********"]
#[inline(always)]
pub fn rom_power_down(&self) -> ROM_POWER_DOWN_R {
ROM_POWER_DOWN_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:13 - ******* Description ***********"]
#[inline(always)]
pub fn sram_power_down(&self) -> SRAM_POWER_DOWN_R {
SRAM_POWER_DOWN_R::new(((self.bits >> 3) & 0x07ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MEM_POWER_DOWN")
.field("rom_power_down", &self.rom_power_down())
.field("sram_power_down", &self.sram_power_down())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - ******* Description ***********"]
#[inline(always)]
pub fn rom_power_down(&mut self) -> ROM_POWER_DOWN_W<MEM_POWER_DOWN_SPEC> {
ROM_POWER_DOWN_W::new(self, 0)
}
#[doc = "Bits 3:13 - ******* Description ***********"]
#[inline(always)]
pub fn sram_power_down(&mut self) -> SRAM_POWER_DOWN_W<MEM_POWER_DOWN_SPEC> {
SRAM_POWER_DOWN_W::new(self, 3)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_power_down::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_power_down::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MEM_POWER_DOWN_SPEC;
impl crate::RegisterSpec for MEM_POWER_DOWN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`mem_power_down::R`](R) reader structure"]
impl crate::Readable for MEM_POWER_DOWN_SPEC {}
#[doc = "`write(|w| ..)` method takes [`mem_power_down::W`](W) writer structure"]
impl crate::Writable for MEM_POWER_DOWN_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MEM_POWER_DOWN to value 0"]
impl crate::Resettable for MEM_POWER_DOWN_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/mem_power_up.rs
Vendored
+62
View File
@@ -0,0 +1,62 @@
#[doc = "Register `MEM_POWER_UP` reader"]
pub type R = crate::R<MEM_POWER_UP_SPEC>;
#[doc = "Register `MEM_POWER_UP` writer"]
pub type W = crate::W<MEM_POWER_UP_SPEC>;
#[doc = "Field `ROM_POWER_UP` reader - ******* Description ***********"]
pub type ROM_POWER_UP_R = crate::FieldReader;
#[doc = "Field `ROM_POWER_UP` writer - ******* Description ***********"]
pub type ROM_POWER_UP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SRAM_POWER_UP` reader - ******* Description ***********"]
pub type SRAM_POWER_UP_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_POWER_UP` writer - ******* Description ***********"]
pub type SRAM_POWER_UP_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - ******* Description ***********"]
#[inline(always)]
pub fn rom_power_up(&self) -> ROM_POWER_UP_R {
ROM_POWER_UP_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:13 - ******* Description ***********"]
#[inline(always)]
pub fn sram_power_up(&self) -> SRAM_POWER_UP_R {
SRAM_POWER_UP_R::new(((self.bits >> 3) & 0x07ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MEM_POWER_UP")
.field("rom_power_up", &self.rom_power_up())
.field("sram_power_up", &self.sram_power_up())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - ******* Description ***********"]
#[inline(always)]
pub fn rom_power_up(&mut self) -> ROM_POWER_UP_W<MEM_POWER_UP_SPEC> {
ROM_POWER_UP_W::new(self, 0)
}
#[doc = "Bits 3:13 - ******* Description ***********"]
#[inline(always)]
pub fn sram_power_up(&mut self) -> SRAM_POWER_UP_W<MEM_POWER_UP_SPEC> {
SRAM_POWER_UP_W::new(self, 3)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_power_up::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_power_up::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MEM_POWER_UP_SPEC;
impl crate::RegisterSpec for MEM_POWER_UP_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`mem_power_up::R`](R) reader structure"]
impl crate::Readable for MEM_POWER_UP_SPEC {}
#[doc = "`write(|w| ..)` method takes [`mem_power_up::W`](W) writer structure"]
impl crate::Writable for MEM_POWER_UP_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MEM_POWER_UP to value 0x3fff"]
impl crate::Resettable for MEM_POWER_UP_SPEC {
const RESET_VALUE: u32 = 0x3fff;
}
vendor/esp32s3/src/apb_ctrl/redcy_sig0.rs
Vendored
+55
View File
@@ -0,0 +1,55 @@
#[doc = "Register `REDCY_SIG0` reader"]
pub type R = crate::R<REDCY_SIG0_SPEC>;
#[doc = "Register `REDCY_SIG0` writer"]
pub type W = crate::W<REDCY_SIG0_SPEC>;
#[doc = "Field `REDCY_SIG0` reader - ******* Description ***********"]
pub type REDCY_SIG0_R = crate::FieldReader<u32>;
#[doc = "Field `REDCY_SIG0` writer - ******* Description ***********"]
pub type REDCY_SIG0_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
#[doc = "Field `REDCY_ANDOR` reader - ******* Description ***********"]
pub type REDCY_ANDOR_R = crate::BitReader;
impl R {
#[doc = "Bits 0:30 - ******* Description ***********"]
#[inline(always)]
pub fn redcy_sig0(&self) -> REDCY_SIG0_R {
REDCY_SIG0_R::new(self.bits & 0x7fff_ffff)
}
#[doc = "Bit 31 - ******* Description ***********"]
#[inline(always)]
pub fn redcy_andor(&self) -> REDCY_ANDOR_R {
REDCY_ANDOR_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("REDCY_SIG0")
.field("redcy_sig0", &self.redcy_sig0())
.field("redcy_andor", &self.redcy_andor())
.finish()
}
}
impl W {
#[doc = "Bits 0:30 - ******* Description ***********"]
#[inline(always)]
pub fn redcy_sig0(&mut self) -> REDCY_SIG0_W<REDCY_SIG0_SPEC> {
REDCY_SIG0_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`redcy_sig0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`redcy_sig0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct REDCY_SIG0_SPEC;
impl crate::RegisterSpec for REDCY_SIG0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`redcy_sig0::R`](R) reader structure"]
impl crate::Readable for REDCY_SIG0_SPEC {}
#[doc = "`write(|w| ..)` method takes [`redcy_sig0::W`](W) writer structure"]
impl crate::Writable for REDCY_SIG0_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets REDCY_SIG0 to value 0"]
impl crate::Resettable for REDCY_SIG0_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/redcy_sig1.rs
Vendored
+55
View File
@@ -0,0 +1,55 @@
#[doc = "Register `REDCY_SIG1` reader"]
pub type R = crate::R<REDCY_SIG1_SPEC>;
#[doc = "Register `REDCY_SIG1` writer"]
pub type W = crate::W<REDCY_SIG1_SPEC>;
#[doc = "Field `REDCY_SIG1` reader - ******* Description ***********"]
pub type REDCY_SIG1_R = crate::FieldReader<u32>;
#[doc = "Field `REDCY_SIG1` writer - ******* Description ***********"]
pub type REDCY_SIG1_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
#[doc = "Field `REDCY_NANDOR` reader - ******* Description ***********"]
pub type REDCY_NANDOR_R = crate::BitReader;
impl R {
#[doc = "Bits 0:30 - ******* Description ***********"]
#[inline(always)]
pub fn redcy_sig1(&self) -> REDCY_SIG1_R {
REDCY_SIG1_R::new(self.bits & 0x7fff_ffff)
}
#[doc = "Bit 31 - ******* Description ***********"]
#[inline(always)]
pub fn redcy_nandor(&self) -> REDCY_NANDOR_R {
REDCY_NANDOR_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("REDCY_SIG1")
.field("redcy_sig1", &self.redcy_sig1())
.field("redcy_nandor", &self.redcy_nandor())
.finish()
}
}
impl W {
#[doc = "Bits 0:30 - ******* Description ***********"]
#[inline(always)]
pub fn redcy_sig1(&mut self) -> REDCY_SIG1_W<REDCY_SIG1_SPEC> {
REDCY_SIG1_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`redcy_sig1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`redcy_sig1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct REDCY_SIG1_SPEC;
impl crate::RegisterSpec for REDCY_SIG1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`redcy_sig1::R`](R) reader structure"]
impl crate::Readable for REDCY_SIG1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`redcy_sig1::W`](W) writer structure"]
impl crate::Writable for REDCY_SIG1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets REDCY_SIG1 to value 0"]
impl crate::Resettable for REDCY_SIG1_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/retention_ctrl.rs
Vendored
+62
View File
@@ -0,0 +1,62 @@
#[doc = "Register `RETENTION_CTRL` reader"]
pub type R = crate::R<RETENTION_CTRL_SPEC>;
#[doc = "Register `RETENTION_CTRL` writer"]
pub type W = crate::W<RETENTION_CTRL_SPEC>;
#[doc = "Field `RETENTION_CPU_LINK_ADDR` reader - ******* Description ***********"]
pub type RETENTION_CPU_LINK_ADDR_R = crate::FieldReader<u32>;
#[doc = "Field `RETENTION_CPU_LINK_ADDR` writer - ******* Description ***********"]
pub type RETENTION_CPU_LINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
#[doc = "Field `NOBYPASS_CPU_ISO_RST` reader - ******* Description ***********"]
pub type NOBYPASS_CPU_ISO_RST_R = crate::BitReader;
#[doc = "Field `NOBYPASS_CPU_ISO_RST` writer - ******* Description ***********"]
pub type NOBYPASS_CPU_ISO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:26 - ******* Description ***********"]
#[inline(always)]
pub fn retention_cpu_link_addr(&self) -> RETENTION_CPU_LINK_ADDR_R {
RETENTION_CPU_LINK_ADDR_R::new(self.bits & 0x07ff_ffff)
}
#[doc = "Bit 27 - ******* Description ***********"]
#[inline(always)]
pub fn nobypass_cpu_iso_rst(&self) -> NOBYPASS_CPU_ISO_RST_R {
NOBYPASS_CPU_ISO_RST_R::new(((self.bits >> 27) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RETENTION_CTRL")
.field("retention_cpu_link_addr", &self.retention_cpu_link_addr())
.field("nobypass_cpu_iso_rst", &self.nobypass_cpu_iso_rst())
.finish()
}
}
impl W {
#[doc = "Bits 0:26 - ******* Description ***********"]
#[inline(always)]
pub fn retention_cpu_link_addr(&mut self) -> RETENTION_CPU_LINK_ADDR_W<RETENTION_CTRL_SPEC> {
RETENTION_CPU_LINK_ADDR_W::new(self, 0)
}
#[doc = "Bit 27 - ******* Description ***********"]
#[inline(always)]
pub fn nobypass_cpu_iso_rst(&mut self) -> NOBYPASS_CPU_ISO_RST_W<RETENTION_CTRL_SPEC> {
NOBYPASS_CPU_ISO_RST_W::new(self, 27)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RETENTION_CTRL_SPEC;
impl crate::RegisterSpec for RETENTION_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`retention_ctrl::R`](R) reader structure"]
impl crate::Readable for RETENTION_CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`retention_ctrl::W`](W) writer structure"]
impl crate::Writable for RETENTION_CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RETENTION_CTRL to value 0"]
impl crate::Resettable for RETENTION_CTRL_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/retention_ctrl1.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `RETENTION_CTRL1` reader"]
pub type R = crate::R<RETENTION_CTRL1_SPEC>;
#[doc = "Register `RETENTION_CTRL1` writer"]
pub type W = crate::W<RETENTION_CTRL1_SPEC>;
#[doc = "Field `RETENTION_TAG_LINK_ADDR` reader - ******* Description ***********"]
pub type RETENTION_TAG_LINK_ADDR_R = crate::FieldReader<u32>;
#[doc = "Field `RETENTION_TAG_LINK_ADDR` writer - ******* Description ***********"]
pub type RETENTION_TAG_LINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:26 - ******* Description ***********"]
#[inline(always)]
pub fn retention_tag_link_addr(&self) -> RETENTION_TAG_LINK_ADDR_R {
RETENTION_TAG_LINK_ADDR_R::new(self.bits & 0x07ff_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RETENTION_CTRL1")
.field("retention_tag_link_addr", &self.retention_tag_link_addr())
.finish()
}
}
impl W {
#[doc = "Bits 0:26 - ******* Description ***********"]
#[inline(always)]
pub fn retention_tag_link_addr(&mut self) -> RETENTION_TAG_LINK_ADDR_W<RETENTION_CTRL1_SPEC> {
RETENTION_TAG_LINK_ADDR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RETENTION_CTRL1_SPEC;
impl crate::RegisterSpec for RETENTION_CTRL1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`retention_ctrl1::R`](R) reader structure"]
impl crate::Readable for RETENTION_CTRL1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`retention_ctrl1::W`](W) writer structure"]
impl crate::Writable for RETENTION_CTRL1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RETENTION_CTRL1 to value 0"]
impl crate::Resettable for RETENTION_CTRL1_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/retention_ctrl2.rs
Vendored
+92
View File
@@ -0,0 +1,92 @@
#[doc = "Register `RETENTION_CTRL2` reader"]
pub type R = crate::R<RETENTION_CTRL2_SPEC>;
#[doc = "Register `RETENTION_CTRL2` writer"]
pub type W = crate::W<RETENTION_CTRL2_SPEC>;
#[doc = "Field `RET_ICACHE_SIZE` reader - ******* Description ***********"]
pub type RET_ICACHE_SIZE_R = crate::FieldReader;
#[doc = "Field `RET_ICACHE_SIZE` writer - ******* Description ***********"]
pub type RET_ICACHE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RET_ICACHE_VLD_SIZE` reader - ******* Description ***********"]
pub type RET_ICACHE_VLD_SIZE_R = crate::FieldReader;
#[doc = "Field `RET_ICACHE_VLD_SIZE` writer - ******* Description ***********"]
pub type RET_ICACHE_VLD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RET_ICACHE_START_POINT` reader - ******* Description ***********"]
pub type RET_ICACHE_START_POINT_R = crate::FieldReader;
#[doc = "Field `RET_ICACHE_START_POINT` writer - ******* Description ***********"]
pub type RET_ICACHE_START_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RET_ICACHE_ENABLE` reader - ******* Description ***********"]
pub type RET_ICACHE_ENABLE_R = crate::BitReader;
#[doc = "Field `RET_ICACHE_ENABLE` writer - ******* Description ***********"]
pub type RET_ICACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 4:11 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_size(&self) -> RET_ICACHE_SIZE_R {
RET_ICACHE_SIZE_R::new(((self.bits >> 4) & 0xff) as u8)
}
#[doc = "Bits 13:20 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_vld_size(&self) -> RET_ICACHE_VLD_SIZE_R {
RET_ICACHE_VLD_SIZE_R::new(((self.bits >> 13) & 0xff) as u8)
}
#[doc = "Bits 22:29 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_start_point(&self) -> RET_ICACHE_START_POINT_R {
RET_ICACHE_START_POINT_R::new(((self.bits >> 22) & 0xff) as u8)
}
#[doc = "Bit 31 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_enable(&self) -> RET_ICACHE_ENABLE_R {
RET_ICACHE_ENABLE_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RETENTION_CTRL2")
.field("ret_icache_size", &self.ret_icache_size())
.field("ret_icache_vld_size", &self.ret_icache_vld_size())
.field("ret_icache_start_point", &self.ret_icache_start_point())
.field("ret_icache_enable", &self.ret_icache_enable())
.finish()
}
}
impl W {
#[doc = "Bits 4:11 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_size(&mut self) -> RET_ICACHE_SIZE_W<RETENTION_CTRL2_SPEC> {
RET_ICACHE_SIZE_W::new(self, 4)
}
#[doc = "Bits 13:20 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_vld_size(&mut self) -> RET_ICACHE_VLD_SIZE_W<RETENTION_CTRL2_SPEC> {
RET_ICACHE_VLD_SIZE_W::new(self, 13)
}
#[doc = "Bits 22:29 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_start_point(&mut self) -> RET_ICACHE_START_POINT_W<RETENTION_CTRL2_SPEC> {
RET_ICACHE_START_POINT_W::new(self, 22)
}
#[doc = "Bit 31 - ******* Description ***********"]
#[inline(always)]
pub fn ret_icache_enable(&mut self) -> RET_ICACHE_ENABLE_W<RETENTION_CTRL2_SPEC> {
RET_ICACHE_ENABLE_W::new(self, 31)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RETENTION_CTRL2_SPEC;
impl crate::RegisterSpec for RETENTION_CTRL2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`retention_ctrl2::R`](R) reader structure"]
impl crate::Readable for RETENTION_CTRL2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`retention_ctrl2::W`](W) writer structure"]
impl crate::Writable for RETENTION_CTRL2_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RETENTION_CTRL2 to value 0x001f_eff0"]
impl crate::Resettable for RETENTION_CTRL2_SPEC {
const RESET_VALUE: u32 = 0x001f_eff0;
}
vendor/esp32s3/src/apb_ctrl/retention_ctrl3.rs
Vendored
+92
View File
@@ -0,0 +1,92 @@
#[doc = "Register `RETENTION_CTRL3` reader"]
pub type R = crate::R<RETENTION_CTRL3_SPEC>;
#[doc = "Register `RETENTION_CTRL3` writer"]
pub type W = crate::W<RETENTION_CTRL3_SPEC>;
#[doc = "Field `RET_DCACHE_SIZE` reader - ******* Description ***********"]
pub type RET_DCACHE_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `RET_DCACHE_SIZE` writer - ******* Description ***********"]
pub type RET_DCACHE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RET_DCACHE_VLD_SIZE` reader - ******* Description ***********"]
pub type RET_DCACHE_VLD_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `RET_DCACHE_VLD_SIZE` writer - ******* Description ***********"]
pub type RET_DCACHE_VLD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RET_DCACHE_START_POINT` reader - ******* Description ***********"]
pub type RET_DCACHE_START_POINT_R = crate::FieldReader<u16>;
#[doc = "Field `RET_DCACHE_START_POINT` writer - ******* Description ***********"]
pub type RET_DCACHE_START_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RET_DCACHE_ENABLE` reader - ******* Description ***********"]
pub type RET_DCACHE_ENABLE_R = crate::BitReader;
#[doc = "Field `RET_DCACHE_ENABLE` writer - ******* Description ***********"]
pub type RET_DCACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 4:12 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_size(&self) -> RET_DCACHE_SIZE_R {
RET_DCACHE_SIZE_R::new(((self.bits >> 4) & 0x01ff) as u16)
}
#[doc = "Bits 13:21 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_vld_size(&self) -> RET_DCACHE_VLD_SIZE_R {
RET_DCACHE_VLD_SIZE_R::new(((self.bits >> 13) & 0x01ff) as u16)
}
#[doc = "Bits 22:30 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_start_point(&self) -> RET_DCACHE_START_POINT_R {
RET_DCACHE_START_POINT_R::new(((self.bits >> 22) & 0x01ff) as u16)
}
#[doc = "Bit 31 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_enable(&self) -> RET_DCACHE_ENABLE_R {
RET_DCACHE_ENABLE_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RETENTION_CTRL3")
.field("ret_dcache_size", &self.ret_dcache_size())
.field("ret_dcache_vld_size", &self.ret_dcache_vld_size())
.field("ret_dcache_start_point", &self.ret_dcache_start_point())
.field("ret_dcache_enable", &self.ret_dcache_enable())
.finish()
}
}
impl W {
#[doc = "Bits 4:12 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_size(&mut self) -> RET_DCACHE_SIZE_W<RETENTION_CTRL3_SPEC> {
RET_DCACHE_SIZE_W::new(self, 4)
}
#[doc = "Bits 13:21 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_vld_size(&mut self) -> RET_DCACHE_VLD_SIZE_W<RETENTION_CTRL3_SPEC> {
RET_DCACHE_VLD_SIZE_W::new(self, 13)
}
#[doc = "Bits 22:30 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_start_point(&mut self) -> RET_DCACHE_START_POINT_W<RETENTION_CTRL3_SPEC> {
RET_DCACHE_START_POINT_W::new(self, 22)
}
#[doc = "Bit 31 - ******* Description ***********"]
#[inline(always)]
pub fn ret_dcache_enable(&mut self) -> RET_DCACHE_ENABLE_W<RETENTION_CTRL3_SPEC> {
RET_DCACHE_ENABLE_W::new(self, 31)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RETENTION_CTRL3_SPEC;
impl crate::RegisterSpec for RETENTION_CTRL3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`retention_ctrl3::R`](R) reader structure"]
impl crate::Readable for RETENTION_CTRL3_SPEC {}
#[doc = "`write(|w| ..)` method takes [`retention_ctrl3::W`](W) writer structure"]
impl crate::Writable for RETENTION_CTRL3_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RETENTION_CTRL3 to value 0x003f_fff0"]
impl crate::Resettable for RETENTION_CTRL3_SPEC {
const RESET_VALUE: u32 = 0x003f_fff0;
}
vendor/esp32s3/src/apb_ctrl/retention_ctrl4.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `RETENTION_CTRL4` reader"]
pub type R = crate::R<RETENTION_CTRL4_SPEC>;
#[doc = "Register `RETENTION_CTRL4` writer"]
pub type W = crate::W<RETENTION_CTRL4_SPEC>;
#[doc = "Field `RETENTION_INV_CFG` reader - ******* Description ***********"]
pub type RETENTION_INV_CFG_R = crate::FieldReader<u32>;
#[doc = "Field `RETENTION_INV_CFG` writer - ******* Description ***********"]
pub type RETENTION_INV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn retention_inv_cfg(&self) -> RETENTION_INV_CFG_R {
RETENTION_INV_CFG_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RETENTION_CTRL4")
.field("retention_inv_cfg", &self.retention_inv_cfg())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn retention_inv_cfg(&mut self) -> RETENTION_INV_CFG_W<RETENTION_CTRL4_SPEC> {
RETENTION_INV_CFG_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RETENTION_CTRL4_SPEC;
impl crate::RegisterSpec for RETENTION_CTRL4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`retention_ctrl4::R`](R) reader structure"]
impl crate::Readable for RETENTION_CTRL4_SPEC {}
#[doc = "`write(|w| ..)` method takes [`retention_ctrl4::W`](W) writer structure"]
impl crate::Writable for RETENTION_CTRL4_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RETENTION_CTRL4 to value 0xffff_ffff"]
impl crate::Resettable for RETENTION_CTRL4_SPEC {
const RESET_VALUE: u32 = 0xffff_ffff;
}
vendor/esp32s3/src/apb_ctrl/retention_ctrl5.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `RETENTION_CTRL5` reader"]
pub type R = crate::R<RETENTION_CTRL5_SPEC>;
#[doc = "Register `RETENTION_CTRL5` writer"]
pub type W = crate::W<RETENTION_CTRL5_SPEC>;
#[doc = "Field `RETENTION_DISABLE` reader - ******* Description ***********"]
pub type RETENTION_DISABLE_R = crate::BitReader;
#[doc = "Field `RETENTION_DISABLE` writer - ******* Description ***********"]
pub type RETENTION_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn retention_disable(&self) -> RETENTION_DISABLE_R {
RETENTION_DISABLE_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RETENTION_CTRL5")
.field("retention_disable", &self.retention_disable())
.finish()
}
}
impl W {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn retention_disable(&mut self) -> RETENTION_DISABLE_W<RETENTION_CTRL5_SPEC> {
RETENTION_DISABLE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RETENTION_CTRL5_SPEC;
impl crate::RegisterSpec for RETENTION_CTRL5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`retention_ctrl5::R`](R) reader structure"]
impl crate::Readable for RETENTION_CTRL5_SPEC {}
#[doc = "`write(|w| ..)` method takes [`retention_ctrl5::W`](W) writer structure"]
impl crate::Writable for RETENTION_CTRL5_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RETENTION_CTRL5 to value 0"]
impl crate::Resettable for RETENTION_CTRL5_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/sdio_ctrl.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SDIO_CTRL` reader"]
pub type R = crate::R<SDIO_CTRL_SPEC>;
#[doc = "Register `SDIO_CTRL` writer"]
pub type W = crate::W<SDIO_CTRL_SPEC>;
#[doc = "Field `SDIO_WIN_ACCESS_EN` reader - ******* Description ***********"]
pub type SDIO_WIN_ACCESS_EN_R = crate::BitReader;
#[doc = "Field `SDIO_WIN_ACCESS_EN` writer - ******* Description ***********"]
pub type SDIO_WIN_ACCESS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn sdio_win_access_en(&self) -> SDIO_WIN_ACCESS_EN_R {
SDIO_WIN_ACCESS_EN_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDIO_CTRL")
.field("sdio_win_access_en", &self.sdio_win_access_en())
.finish()
}
}
impl W {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn sdio_win_access_en(&mut self) -> SDIO_WIN_ACCESS_EN_W<SDIO_CTRL_SPEC> {
SDIO_WIN_ACCESS_EN_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sdio_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdio_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SDIO_CTRL_SPEC;
impl crate::RegisterSpec for SDIO_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sdio_ctrl::R`](R) reader structure"]
impl crate::Readable for SDIO_CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sdio_ctrl::W`](W) writer structure"]
impl crate::Writable for SDIO_CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SDIO_CTRL to value 0"]
impl crate::Resettable for SDIO_CTRL_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
Vendored
+62
View File
@@ -0,0 +1,62 @@
#[doc = "Register `SPI_MEM_ECC_CTRL` reader"]
pub type R = crate::R<SPI_MEM_ECC_CTRL_SPEC>;
#[doc = "Register `SPI_MEM_ECC_CTRL` writer"]
pub type W = crate::W<SPI_MEM_ECC_CTRL_SPEC>;
#[doc = "Field `FLASH_PAGE_SIZE` reader - Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
pub type FLASH_PAGE_SIZE_R = crate::FieldReader;
#[doc = "Field `FLASH_PAGE_SIZE` writer - Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
pub type FLASH_PAGE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SRAM_PAGE_SIZE` reader - Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
pub type SRAM_PAGE_SIZE_R = crate::FieldReader;
#[doc = "Field `SRAM_PAGE_SIZE` writer - Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
pub type SRAM_PAGE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 18:19 - Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
#[inline(always)]
pub fn flash_page_size(&self) -> FLASH_PAGE_SIZE_R {
FLASH_PAGE_SIZE_R::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bits 20:21 - Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
#[inline(always)]
pub fn sram_page_size(&self) -> SRAM_PAGE_SIZE_R {
SRAM_PAGE_SIZE_R::new(((self.bits >> 20) & 3) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI_MEM_ECC_CTRL")
.field("flash_page_size", &self.flash_page_size())
.field("sram_page_size", &self.sram_page_size())
.finish()
}
}
impl W {
#[doc = "Bits 18:19 - Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
#[inline(always)]
pub fn flash_page_size(&mut self) -> FLASH_PAGE_SIZE_W<SPI_MEM_ECC_CTRL_SPEC> {
FLASH_PAGE_SIZE_W::new(self, 18)
}
#[doc = "Bits 20:21 - Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
#[inline(always)]
pub fn sram_page_size(&mut self) -> SRAM_PAGE_SIZE_W<SPI_MEM_ECC_CTRL_SPEC> {
SRAM_PAGE_SIZE_W::new(self, 20)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_mem_ecc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_mem_ecc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPI_MEM_ECC_CTRL_SPEC;
impl crate::RegisterSpec for SPI_MEM_ECC_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi_mem_ecc_ctrl::R`](R) reader structure"]
impl crate::Readable for SPI_MEM_ECC_CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`spi_mem_ecc_ctrl::W`](W) writer structure"]
impl crate::Writable for SPI_MEM_ECC_CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPI_MEM_ECC_CTRL to value 0x0020_0000"]
impl crate::Resettable for SPI_MEM_ECC_CTRL_SPEC {
const RESET_VALUE: u32 = 0x0020_0000;
}
vendor/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
Vendored
+55
View File
@@ -0,0 +1,55 @@
#[doc = "Register `SPI_MEM_PMS_CTRL` reader"]
pub type R = crate::R<SPI_MEM_PMS_CTRL_SPEC>;
#[doc = "Register `SPI_MEM_PMS_CTRL` writer"]
pub type W = crate::W<SPI_MEM_PMS_CTRL_SPEC>;
#[doc = "Field `SPI_MEM_REJECT_INT` reader - ******* Description ***********"]
pub type SPI_MEM_REJECT_INT_R = crate::BitReader;
#[doc = "Field `SPI_MEM_REJECT_CLR` writer - ******* Description ***********"]
pub type SPI_MEM_REJECT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_MEM_REJECT_CDE` reader - ******* Description ***********"]
pub type SPI_MEM_REJECT_CDE_R = crate::FieldReader;
impl R {
#[doc = "Bit 0 - ******* Description ***********"]
#[inline(always)]
pub fn spi_mem_reject_int(&self) -> SPI_MEM_REJECT_INT_R {
SPI_MEM_REJECT_INT_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:6 - ******* Description ***********"]
#[inline(always)]
pub fn spi_mem_reject_cde(&self) -> SPI_MEM_REJECT_CDE_R {
SPI_MEM_REJECT_CDE_R::new(((self.bits >> 2) & 0x1f) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI_MEM_PMS_CTRL")
.field("spi_mem_reject_int", &self.spi_mem_reject_int())
.field("spi_mem_reject_cde", &self.spi_mem_reject_cde())
.finish()
}
}
impl W {
#[doc = "Bit 1 - ******* Description ***********"]
#[inline(always)]
pub fn spi_mem_reject_clr(&mut self) -> SPI_MEM_REJECT_CLR_W<SPI_MEM_PMS_CTRL_SPEC> {
SPI_MEM_REJECT_CLR_W::new(self, 1)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_mem_pms_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_mem_pms_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPI_MEM_PMS_CTRL_SPEC;
impl crate::RegisterSpec for SPI_MEM_PMS_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi_mem_pms_ctrl::R`](R) reader structure"]
impl crate::Readable for SPI_MEM_PMS_CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`spi_mem_pms_ctrl::W`](W) writer structure"]
impl crate::Writable for SPI_MEM_PMS_CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPI_MEM_PMS_CTRL to value 0"]
impl crate::Resettable for SPI_MEM_PMS_CTRL_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/spi_mem_reject_addr.rs
Vendored
+30
View File
@@ -0,0 +1,30 @@
#[doc = "Register `SPI_MEM_REJECT_ADDR` reader"]
pub type R = crate::R<SPI_MEM_REJECT_ADDR_SPEC>;
#[doc = "Field `SPI_MEM_REJECT_ADDR` reader - ******* Description ***********"]
pub type SPI_MEM_REJECT_ADDR_R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn spi_mem_reject_addr(&self) -> SPI_MEM_REJECT_ADDR_R {
SPI_MEM_REJECT_ADDR_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI_MEM_REJECT_ADDR")
.field("spi_mem_reject_addr", &self.spi_mem_reject_addr())
.finish()
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_mem_reject_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPI_MEM_REJECT_ADDR_SPEC;
impl crate::RegisterSpec for SPI_MEM_REJECT_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi_mem_reject_addr::R`](R) reader structure"]
impl crate::Readable for SPI_MEM_REJECT_ADDR_SPEC {}
#[doc = "`reset()` method sets SPI_MEM_REJECT_ADDR to value 0"]
impl crate::Resettable for SPI_MEM_REJECT_ADDR_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE0_ADDR` reader"]
pub type R = crate::R<SRAM_ACE0_ADDR_SPEC>;
#[doc = "Register `SRAM_ACE0_ADDR` writer"]
pub type W = crate::W<SRAM_ACE0_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE0_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<SRAM_ACE0_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE0_ADDR_SPEC;
impl crate::RegisterSpec for SRAM_ACE0_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace0_addr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE0_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace0_addr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE0_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE0_ADDR to value 0"]
impl crate::Resettable for SRAM_ACE0_ADDR_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE0_ATTR` reader"]
pub type R = crate::R<SRAM_ACE0_ATTR_SPEC>;
#[doc = "Register `SRAM_ACE0_ATTR` writer"]
pub type W = crate::W<SRAM_ACE0_ATTR_SPEC>;
#[doc = "Field `SRAM_ACE0_ATTR` reader - ******* Description ***********"]
pub type SRAM_ACE0_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE0_ATTR` writer - ******* Description ***********"]
pub type SRAM_ACE0_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace0_attr(&self) -> SRAM_ACE0_ATTR_R {
SRAM_ACE0_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE0_ATTR")
.field("sram_ace0_attr", &self.sram_ace0_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace0_attr(&mut self) -> SRAM_ACE0_ATTR_W<SRAM_ACE0_ATTR_SPEC> {
SRAM_ACE0_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace0_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace0_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE0_ATTR_SPEC;
impl crate::RegisterSpec for SRAM_ACE0_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace0_attr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE0_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace0_attr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE0_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE0_ATTR to value 0xff"]
impl crate::Resettable for SRAM_ACE0_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/sram_ace0_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE0_SIZE` reader"]
pub type R = crate::R<SRAM_ACE0_SIZE_SPEC>;
#[doc = "Register `SRAM_ACE0_SIZE` writer"]
pub type W = crate::W<SRAM_ACE0_SIZE_SPEC>;
#[doc = "Field `SRAM_ACE0_SIZE` reader - ******* Description ***********"]
pub type SRAM_ACE0_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE0_SIZE` writer - ******* Description ***********"]
pub type SRAM_ACE0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace0_size(&self) -> SRAM_ACE0_SIZE_R {
SRAM_ACE0_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE0_SIZE")
.field("sram_ace0_size", &self.sram_ace0_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace0_size(&mut self) -> SRAM_ACE0_SIZE_W<SRAM_ACE0_SIZE_SPEC> {
SRAM_ACE0_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace0_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace0_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE0_SIZE_SPEC;
impl crate::RegisterSpec for SRAM_ACE0_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace0_size::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE0_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace0_size::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE0_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE0_SIZE to value 0x1000"]
impl crate::Resettable for SRAM_ACE0_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE1_ADDR` reader"]
pub type R = crate::R<SRAM_ACE1_ADDR_SPEC>;
#[doc = "Register `SRAM_ACE1_ADDR` writer"]
pub type W = crate::W<SRAM_ACE1_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE1_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<SRAM_ACE1_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE1_ADDR_SPEC;
impl crate::RegisterSpec for SRAM_ACE1_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace1_addr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE1_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace1_addr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE1_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE1_ADDR to value 0x1000_0000"]
impl crate::Resettable for SRAM_ACE1_ADDR_SPEC {
const RESET_VALUE: u32 = 0x1000_0000;
}
vendor/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE1_ATTR` reader"]
pub type R = crate::R<SRAM_ACE1_ATTR_SPEC>;
#[doc = "Register `SRAM_ACE1_ATTR` writer"]
pub type W = crate::W<SRAM_ACE1_ATTR_SPEC>;
#[doc = "Field `SRAM_ACE1_ATTR` reader - ******* Description ***********"]
pub type SRAM_ACE1_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE1_ATTR` writer - ******* Description ***********"]
pub type SRAM_ACE1_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace1_attr(&self) -> SRAM_ACE1_ATTR_R {
SRAM_ACE1_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE1_ATTR")
.field("sram_ace1_attr", &self.sram_ace1_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace1_attr(&mut self) -> SRAM_ACE1_ATTR_W<SRAM_ACE1_ATTR_SPEC> {
SRAM_ACE1_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace1_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace1_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE1_ATTR_SPEC;
impl crate::RegisterSpec for SRAM_ACE1_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace1_attr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE1_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace1_attr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE1_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE1_ATTR to value 0xff"]
impl crate::Resettable for SRAM_ACE1_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/sram_ace1_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE1_SIZE` reader"]
pub type R = crate::R<SRAM_ACE1_SIZE_SPEC>;
#[doc = "Register `SRAM_ACE1_SIZE` writer"]
pub type W = crate::W<SRAM_ACE1_SIZE_SPEC>;
#[doc = "Field `SRAM_ACE1_SIZE` reader - ******* Description ***********"]
pub type SRAM_ACE1_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE1_SIZE` writer - ******* Description ***********"]
pub type SRAM_ACE1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace1_size(&self) -> SRAM_ACE1_SIZE_R {
SRAM_ACE1_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE1_SIZE")
.field("sram_ace1_size", &self.sram_ace1_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace1_size(&mut self) -> SRAM_ACE1_SIZE_W<SRAM_ACE1_SIZE_SPEC> {
SRAM_ACE1_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace1_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace1_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE1_SIZE_SPEC;
impl crate::RegisterSpec for SRAM_ACE1_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace1_size::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE1_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace1_size::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE1_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE1_SIZE to value 0x1000"]
impl crate::Resettable for SRAM_ACE1_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE2_ADDR` reader"]
pub type R = crate::R<SRAM_ACE2_ADDR_SPEC>;
#[doc = "Register `SRAM_ACE2_ADDR` writer"]
pub type W = crate::W<SRAM_ACE2_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE2_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<SRAM_ACE2_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace2_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace2_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE2_ADDR_SPEC;
impl crate::RegisterSpec for SRAM_ACE2_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace2_addr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE2_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace2_addr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE2_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE2_ADDR to value 0x2000_0000"]
impl crate::Resettable for SRAM_ACE2_ADDR_SPEC {
const RESET_VALUE: u32 = 0x2000_0000;
}
vendor/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE2_ATTR` reader"]
pub type R = crate::R<SRAM_ACE2_ATTR_SPEC>;
#[doc = "Register `SRAM_ACE2_ATTR` writer"]
pub type W = crate::W<SRAM_ACE2_ATTR_SPEC>;
#[doc = "Field `SRAM_ACE2_ATTR` reader - ******* Description ***********"]
pub type SRAM_ACE2_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE2_ATTR` writer - ******* Description ***********"]
pub type SRAM_ACE2_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace2_attr(&self) -> SRAM_ACE2_ATTR_R {
SRAM_ACE2_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE2_ATTR")
.field("sram_ace2_attr", &self.sram_ace2_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace2_attr(&mut self) -> SRAM_ACE2_ATTR_W<SRAM_ACE2_ATTR_SPEC> {
SRAM_ACE2_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace2_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace2_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE2_ATTR_SPEC;
impl crate::RegisterSpec for SRAM_ACE2_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace2_attr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE2_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace2_attr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE2_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE2_ATTR to value 0xff"]
impl crate::Resettable for SRAM_ACE2_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/sram_ace2_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE2_SIZE` reader"]
pub type R = crate::R<SRAM_ACE2_SIZE_SPEC>;
#[doc = "Register `SRAM_ACE2_SIZE` writer"]
pub type W = crate::W<SRAM_ACE2_SIZE_SPEC>;
#[doc = "Field `SRAM_ACE2_SIZE` reader - ******* Description ***********"]
pub type SRAM_ACE2_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE2_SIZE` writer - ******* Description ***********"]
pub type SRAM_ACE2_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace2_size(&self) -> SRAM_ACE2_SIZE_R {
SRAM_ACE2_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE2_SIZE")
.field("sram_ace2_size", &self.sram_ace2_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace2_size(&mut self) -> SRAM_ACE2_SIZE_W<SRAM_ACE2_SIZE_SPEC> {
SRAM_ACE2_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace2_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace2_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE2_SIZE_SPEC;
impl crate::RegisterSpec for SRAM_ACE2_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace2_size::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE2_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace2_size::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE2_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE2_SIZE to value 0x1000"]
impl crate::Resettable for SRAM_ACE2_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE3_ADDR` reader"]
pub type R = crate::R<SRAM_ACE3_ADDR_SPEC>;
#[doc = "Register `SRAM_ACE3_ADDR` writer"]
pub type W = crate::W<SRAM_ACE3_ADDR_SPEC>;
#[doc = "Field `S` reader - ******* Description ***********"]
pub type S_R = crate::FieldReader<u32>;
#[doc = "Field `S` writer - ******* Description ***********"]
pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&self) -> S_R {
S_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE3_ADDR")
.field("s", &self.s())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn s(&mut self) -> S_W<SRAM_ACE3_ADDR_SPEC> {
S_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace3_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace3_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE3_ADDR_SPEC;
impl crate::RegisterSpec for SRAM_ACE3_ADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace3_addr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE3_ADDR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace3_addr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE3_ADDR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE3_ADDR to value 0x3000_0000"]
impl crate::Resettable for SRAM_ACE3_ADDR_SPEC {
const RESET_VALUE: u32 = 0x3000_0000;
}
vendor/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE3_ATTR` reader"]
pub type R = crate::R<SRAM_ACE3_ATTR_SPEC>;
#[doc = "Register `SRAM_ACE3_ATTR` writer"]
pub type W = crate::W<SRAM_ACE3_ATTR_SPEC>;
#[doc = "Field `SRAM_ACE3_ATTR` reader - ******* Description ***********"]
pub type SRAM_ACE3_ATTR_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE3_ATTR` writer - ******* Description ***********"]
pub type SRAM_ACE3_ATTR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
impl R {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace3_attr(&self) -> SRAM_ACE3_ATTR_R {
SRAM_ACE3_ATTR_R::new((self.bits & 0x01ff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE3_ATTR")
.field("sram_ace3_attr", &self.sram_ace3_attr())
.finish()
}
}
impl W {
#[doc = "Bits 0:8 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace3_attr(&mut self) -> SRAM_ACE3_ATTR_W<SRAM_ACE3_ATTR_SPEC> {
SRAM_ACE3_ATTR_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace3_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace3_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE3_ATTR_SPEC;
impl crate::RegisterSpec for SRAM_ACE3_ATTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace3_attr::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE3_ATTR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace3_attr::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE3_ATTR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE3_ATTR to value 0xff"]
impl crate::Resettable for SRAM_ACE3_ATTR_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_ctrl/sram_ace3_size.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SRAM_ACE3_SIZE` reader"]
pub type R = crate::R<SRAM_ACE3_SIZE_SPEC>;
#[doc = "Register `SRAM_ACE3_SIZE` writer"]
pub type W = crate::W<SRAM_ACE3_SIZE_SPEC>;
#[doc = "Field `SRAM_ACE3_SIZE` reader - ******* Description ***********"]
pub type SRAM_ACE3_SIZE_R = crate::FieldReader<u16>;
#[doc = "Field `SRAM_ACE3_SIZE` writer - ******* Description ***********"]
pub type SRAM_ACE3_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace3_size(&self) -> SRAM_ACE3_SIZE_R {
SRAM_ACE3_SIZE_R::new((self.bits & 0xffff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SRAM_ACE3_SIZE")
.field("sram_ace3_size", &self.sram_ace3_size())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ******* Description ***********"]
#[inline(always)]
pub fn sram_ace3_size(&mut self) -> SRAM_ACE3_SIZE_W<SRAM_ACE3_SIZE_SPEC> {
SRAM_ACE3_SIZE_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ace3_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ace3_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAM_ACE3_SIZE_SPEC;
impl crate::RegisterSpec for SRAM_ACE3_SIZE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sram_ace3_size::R`](R) reader structure"]
impl crate::Readable for SRAM_ACE3_SIZE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sram_ace3_size::W`](W) writer structure"]
impl crate::Writable for SRAM_ACE3_SIZE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SRAM_ACE3_SIZE to value 0x1000"]
impl crate::Resettable for SRAM_ACE3_SIZE_SPEC {
const RESET_VALUE: u32 = 0x1000;
}
vendor/esp32s3/src/apb_ctrl/sysclk_conf.rs
Vendored
+92
View File
@@ -0,0 +1,92 @@
#[doc = "Register `SYSCLK_CONF` reader"]
pub type R = crate::R<SYSCLK_CONF_SPEC>;
#[doc = "Register `SYSCLK_CONF` writer"]
pub type W = crate::W<SYSCLK_CONF_SPEC>;
#[doc = "Field `PRE_DIV_CNT` reader - ******* Description ***********"]
pub type PRE_DIV_CNT_R = crate::FieldReader<u16>;
#[doc = "Field `PRE_DIV_CNT` writer - ******* Description ***********"]
pub type PRE_DIV_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `CLK_320M_EN` reader - ******* Description ***********"]
pub type CLK_320M_EN_R = crate::BitReader;
#[doc = "Field `CLK_320M_EN` writer - ******* Description ***********"]
pub type CLK_320M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_EN` reader - ******* Description ***********"]
pub type CLK_EN_R = crate::BitReader;
#[doc = "Field `CLK_EN` writer - ******* Description ***********"]
pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST_TICK_CNT` reader - ******* Description ***********"]
pub type RST_TICK_CNT_R = crate::BitReader;
#[doc = "Field `RST_TICK_CNT` writer - ******* Description ***********"]
pub type RST_TICK_CNT_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9 - ******* Description ***********"]
#[inline(always)]
pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R {
PRE_DIV_CNT_R::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10 - ******* Description ***********"]
#[inline(always)]
pub fn clk_320m_en(&self) -> CLK_320M_EN_R {
CLK_320M_EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - ******* Description ***********"]
#[inline(always)]
pub fn clk_en(&self) -> CLK_EN_R {
CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - ******* Description ***********"]
#[inline(always)]
pub fn rst_tick_cnt(&self) -> RST_TICK_CNT_R {
RST_TICK_CNT_R::new(((self.bits >> 12) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCLK_CONF")
.field("pre_div_cnt", &self.pre_div_cnt())
.field("clk_320m_en", &self.clk_320m_en())
.field("clk_en", &self.clk_en())
.field("rst_tick_cnt", &self.rst_tick_cnt())
.finish()
}
}
impl W {
#[doc = "Bits 0:9 - ******* Description ***********"]
#[inline(always)]
pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
PRE_DIV_CNT_W::new(self, 0)
}
#[doc = "Bit 10 - ******* Description ***********"]
#[inline(always)]
pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
CLK_320M_EN_W::new(self, 10)
}
#[doc = "Bit 11 - ******* Description ***********"]
#[inline(always)]
pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
CLK_EN_W::new(self, 11)
}
#[doc = "Bit 12 - ******* Description ***********"]
#[inline(always)]
pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
RST_TICK_CNT_W::new(self, 12)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SYSCLK_CONF_SPEC;
impl crate::RegisterSpec for SYSCLK_CONF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sysclk_conf::R`](R) reader structure"]
impl crate::Readable for SYSCLK_CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sysclk_conf::W`](W) writer structure"]
impl crate::Writable for SYSCLK_CONF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SYSCLK_CONF to value 0x01"]
impl crate::Resettable for SYSCLK_CONF_SPEC {
const RESET_VALUE: u32 = 0x01;
}
vendor/esp32s3/src/apb_ctrl/tick_conf.rs
Vendored
+77
View File
@@ -0,0 +1,77 @@
#[doc = "Register `TICK_CONF` reader"]
pub type R = crate::R<TICK_CONF_SPEC>;
#[doc = "Register `TICK_CONF` writer"]
pub type W = crate::W<TICK_CONF_SPEC>;
#[doc = "Field `XTAL_TICK_NUM` reader - ******* Description ***********"]
pub type XTAL_TICK_NUM_R = crate::FieldReader;
#[doc = "Field `XTAL_TICK_NUM` writer - ******* Description ***********"]
pub type XTAL_TICK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `CK8M_TICK_NUM` reader - ******* Description ***********"]
pub type CK8M_TICK_NUM_R = crate::FieldReader;
#[doc = "Field `CK8M_TICK_NUM` writer - ******* Description ***********"]
pub type CK8M_TICK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `TICK_ENABLE` reader - ******* Description ***********"]
pub type TICK_ENABLE_R = crate::BitReader;
#[doc = "Field `TICK_ENABLE` writer - ******* Description ***********"]
pub type TICK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:7 - ******* Description ***********"]
#[inline(always)]
pub fn xtal_tick_num(&self) -> XTAL_TICK_NUM_R {
XTAL_TICK_NUM_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - ******* Description ***********"]
#[inline(always)]
pub fn ck8m_tick_num(&self) -> CK8M_TICK_NUM_R {
CK8M_TICK_NUM_R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bit 16 - ******* Description ***********"]
#[inline(always)]
pub fn tick_enable(&self) -> TICK_ENABLE_R {
TICK_ENABLE_R::new(((self.bits >> 16) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TICK_CONF")
.field("xtal_tick_num", &self.xtal_tick_num())
.field("ck8m_tick_num", &self.ck8m_tick_num())
.field("tick_enable", &self.tick_enable())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - ******* Description ***********"]
#[inline(always)]
pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<TICK_CONF_SPEC> {
XTAL_TICK_NUM_W::new(self, 0)
}
#[doc = "Bits 8:15 - ******* Description ***********"]
#[inline(always)]
pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<TICK_CONF_SPEC> {
CK8M_TICK_NUM_W::new(self, 8)
}
#[doc = "Bit 16 - ******* Description ***********"]
#[inline(always)]
pub fn tick_enable(&mut self) -> TICK_ENABLE_W<TICK_CONF_SPEC> {
TICK_ENABLE_W::new(self, 16)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`tick_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tick_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TICK_CONF_SPEC;
impl crate::RegisterSpec for TICK_CONF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`tick_conf::R`](R) reader structure"]
impl crate::Readable for TICK_CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`tick_conf::W`](W) writer structure"]
impl crate::Writable for TICK_CONF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TICK_CONF to value 0x0001_0727"]
impl crate::Resettable for TICK_CONF_SPEC {
const RESET_VALUE: u32 = 0x0001_0727;
}
vendor/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `WIFI_BB_CFG` reader"]
pub type R = crate::R<WIFI_BB_CFG_SPEC>;
#[doc = "Register `WIFI_BB_CFG` writer"]
pub type W = crate::W<WIFI_BB_CFG_SPEC>;
#[doc = "Field `WIFI_BB_CFG` reader - ******* Description ***********"]
pub type WIFI_BB_CFG_R = crate::FieldReader<u32>;
#[doc = "Field `WIFI_BB_CFG` writer - ******* Description ***********"]
pub type WIFI_BB_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_bb_cfg(&self) -> WIFI_BB_CFG_R {
WIFI_BB_CFG_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WIFI_BB_CFG")
.field("wifi_bb_cfg", &self.wifi_bb_cfg())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_bb_cfg(&mut self) -> WIFI_BB_CFG_W<WIFI_BB_CFG_SPEC> {
WIFI_BB_CFG_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_bb_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_bb_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WIFI_BB_CFG_SPEC;
impl crate::RegisterSpec for WIFI_BB_CFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`wifi_bb_cfg::R`](R) reader structure"]
impl crate::Readable for WIFI_BB_CFG_SPEC {}
#[doc = "`write(|w| ..)` method takes [`wifi_bb_cfg::W`](W) writer structure"]
impl crate::Writable for WIFI_BB_CFG_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WIFI_BB_CFG to value 0"]
impl crate::Resettable for WIFI_BB_CFG_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `WIFI_BB_CFG_2` reader"]
pub type R = crate::R<WIFI_BB_CFG_2_SPEC>;
#[doc = "Register `WIFI_BB_CFG_2` writer"]
pub type W = crate::W<WIFI_BB_CFG_2_SPEC>;
#[doc = "Field `WIFI_BB_CFG_2` reader - ******* Description ***********"]
pub type WIFI_BB_CFG_2_R = crate::FieldReader<u32>;
#[doc = "Field `WIFI_BB_CFG_2` writer - ******* Description ***********"]
pub type WIFI_BB_CFG_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_bb_cfg_2(&self) -> WIFI_BB_CFG_2_R {
WIFI_BB_CFG_2_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WIFI_BB_CFG_2")
.field("wifi_bb_cfg_2", &self.wifi_bb_cfg_2())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_bb_cfg_2(&mut self) -> WIFI_BB_CFG_2_W<WIFI_BB_CFG_2_SPEC> {
WIFI_BB_CFG_2_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_bb_cfg_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_bb_cfg_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WIFI_BB_CFG_2_SPEC;
impl crate::RegisterSpec for WIFI_BB_CFG_2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`wifi_bb_cfg_2::R`](R) reader structure"]
impl crate::Readable for WIFI_BB_CFG_2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`wifi_bb_cfg_2::W`](W) writer structure"]
impl crate::Writable for WIFI_BB_CFG_2_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WIFI_BB_CFG_2 to value 0"]
impl crate::Resettable for WIFI_BB_CFG_2_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_ctrl/wifi_clk_en.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `WIFI_CLK_EN` reader"]
pub type R = crate::R<WIFI_CLK_EN_SPEC>;
#[doc = "Register `WIFI_CLK_EN` writer"]
pub type W = crate::W<WIFI_CLK_EN_SPEC>;
#[doc = "Field `WIFI_CLK_EN` reader - ******* Description ***********"]
pub type WIFI_CLK_EN_R = crate::FieldReader<u32>;
#[doc = "Field `WIFI_CLK_EN` writer - ******* Description ***********"]
pub type WIFI_CLK_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_clk_en(&self) -> WIFI_CLK_EN_R {
WIFI_CLK_EN_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WIFI_CLK_EN")
.field("wifi_clk_en", &self.wifi_clk_en())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_clk_en(&mut self) -> WIFI_CLK_EN_W<WIFI_CLK_EN_SPEC> {
WIFI_CLK_EN_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WIFI_CLK_EN_SPEC;
impl crate::RegisterSpec for WIFI_CLK_EN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`wifi_clk_en::R`](R) reader structure"]
impl crate::Readable for WIFI_CLK_EN_SPEC {}
#[doc = "`write(|w| ..)` method takes [`wifi_clk_en::W`](W) writer structure"]
impl crate::Writable for WIFI_CLK_EN_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WIFI_CLK_EN to value 0xfffc_e030"]
impl crate::Resettable for WIFI_CLK_EN_SPEC {
const RESET_VALUE: u32 = 0xfffc_e030;
}
vendor/esp32s3/src/apb_ctrl/wifi_rst_en.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `WIFI_RST_EN` reader"]
pub type R = crate::R<WIFI_RST_EN_SPEC>;
#[doc = "Register `WIFI_RST_EN` writer"]
pub type W = crate::W<WIFI_RST_EN_SPEC>;
#[doc = "Field `WIFI_RST` reader - ******* Description ***********"]
pub type WIFI_RST_R = crate::FieldReader<u32>;
#[doc = "Field `WIFI_RST` writer - ******* Description ***********"]
pub type WIFI_RST_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_rst(&self) -> WIFI_RST_R {
WIFI_RST_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WIFI_RST_EN")
.field("wifi_rst", &self.wifi_rst())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - ******* Description ***********"]
#[inline(always)]
pub fn wifi_rst(&mut self) -> WIFI_RST_W<WIFI_RST_EN_SPEC> {
WIFI_RST_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_rst_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_rst_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WIFI_RST_EN_SPEC;
impl crate::RegisterSpec for WIFI_RST_EN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`wifi_rst_en::R`](R) reader structure"]
impl crate::Readable for WIFI_RST_EN_SPEC {}
#[doc = "`write(|w| ..)` method takes [`wifi_rst_en::W`](W) writer structure"]
impl crate::Writable for WIFI_RST_EN_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WIFI_RST_EN to value 0"]
impl crate::Resettable for WIFI_RST_EN_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc.rs
Vendored
+292
View File
@@ -0,0 +1,292 @@
#[repr(C)]
#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
#[doc = "Register block"]
pub struct RegisterBlock {
ctrl: CTRL,
ctrl2: CTRL2,
filter_ctrl1: FILTER_CTRL1,
fsm_wait: FSM_WAIT,
sar1_status: SAR1_STATUS,
sar2_status: SAR2_STATUS,
sar1_patt_tab1: SAR1_PATT_TAB1,
sar1_patt_tab2: SAR1_PATT_TAB2,
sar1_patt_tab3: SAR1_PATT_TAB3,
sar1_patt_tab4: SAR1_PATT_TAB4,
sar2_patt_tab1: SAR2_PATT_TAB1,
sar2_patt_tab2: SAR2_PATT_TAB2,
sar2_patt_tab3: SAR2_PATT_TAB3,
sar2_patt_tab4: SAR2_PATT_TAB4,
arb_ctrl: ARB_CTRL,
filter_ctrl0: FILTER_CTRL0,
apb_saradc1_data_status: APB_SARADC1_DATA_STATUS,
thres0_ctrl: THRES0_CTRL,
thres1_ctrl: THRES1_CTRL,
_reserved19: [u8; 0x0c],
thres_ctrl: THRES_CTRL,
int_ena: INT_ENA,
int_raw: INT_RAW,
int_st: INT_ST,
int_clr: INT_CLR,
dma_conf: DMA_CONF,
clkm_conf: CLKM_CONF,
_reserved26: [u8; 0x04],
apb_saradc2_data_status: APB_SARADC2_DATA_STATUS,
_reserved27: [u8; 0x0380],
ctrl_date: CTRL_DATE,
}
impl RegisterBlock {
#[doc = "0x00 - configure apb saradc controller"]
#[inline(always)]
pub const fn ctrl(&self) -> &CTRL {
&self.ctrl
}
#[doc = "0x04 - configure apb saradc controller"]
#[inline(always)]
pub const fn ctrl2(&self) -> &CTRL2 {
&self.ctrl2
}
#[doc = "0x08 - configure saradc filter"]
#[inline(always)]
pub const fn filter_ctrl1(&self) -> &FILTER_CTRL1 {
&self.filter_ctrl1
}
#[doc = "0x0c - configure apb saradc fsm"]
#[inline(always)]
pub const fn fsm_wait(&self) -> &FSM_WAIT {
&self.fsm_wait
}
#[doc = "0x10 - saradc1 status for debug"]
#[inline(always)]
pub const fn sar1_status(&self) -> &SAR1_STATUS {
&self.sar1_status
}
#[doc = "0x14 - saradc2 status for debug"]
#[inline(always)]
pub const fn sar2_status(&self) -> &SAR2_STATUS {
&self.sar2_status
}
#[doc = "0x18 - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar1_patt_tab1(&self) -> &SAR1_PATT_TAB1 {
&self.sar1_patt_tab1
}
#[doc = "0x1c - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar1_patt_tab2(&self) -> &SAR1_PATT_TAB2 {
&self.sar1_patt_tab2
}
#[doc = "0x20 - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar1_patt_tab3(&self) -> &SAR1_PATT_TAB3 {
&self.sar1_patt_tab3
}
#[doc = "0x24 - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar1_patt_tab4(&self) -> &SAR1_PATT_TAB4 {
&self.sar1_patt_tab4
}
#[doc = "0x28 - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar2_patt_tab1(&self) -> &SAR2_PATT_TAB1 {
&self.sar2_patt_tab1
}
#[doc = "0x2c - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar2_patt_tab2(&self) -> &SAR2_PATT_TAB2 {
&self.sar2_patt_tab2
}
#[doc = "0x30 - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar2_patt_tab3(&self) -> &SAR2_PATT_TAB3 {
&self.sar2_patt_tab3
}
#[doc = "0x34 - configure apb saradc pattern table"]
#[inline(always)]
pub const fn sar2_patt_tab4(&self) -> &SAR2_PATT_TAB4 {
&self.sar2_patt_tab4
}
#[doc = "0x38 - configure apb saradc arbit"]
#[inline(always)]
pub const fn arb_ctrl(&self) -> &ARB_CTRL {
&self.arb_ctrl
}
#[doc = "0x3c - configure apb saradc arbit"]
#[inline(always)]
pub const fn filter_ctrl0(&self) -> &FILTER_CTRL0 {
&self.filter_ctrl0
}
#[doc = "0x40 - get apb saradc sample data"]
#[inline(always)]
pub const fn apb_saradc1_data_status(&self) -> &APB_SARADC1_DATA_STATUS {
&self.apb_saradc1_data_status
}
#[doc = "0x44 - configure apb saradc thres monitor"]
#[inline(always)]
pub const fn thres0_ctrl(&self) -> &THRES0_CTRL {
&self.thres0_ctrl
}
#[doc = "0x48 - configure apb saradc thres monitor"]
#[inline(always)]
pub const fn thres1_ctrl(&self) -> &THRES1_CTRL {
&self.thres1_ctrl
}
#[doc = "0x58 - configure thres monitor enable"]
#[inline(always)]
pub const fn thres_ctrl(&self) -> &THRES_CTRL {
&self.thres_ctrl
}
#[doc = "0x5c - enable interrupt"]
#[inline(always)]
pub const fn int_ena(&self) -> &INT_ENA {
&self.int_ena
}
#[doc = "0x60 - raw of interrupt"]
#[inline(always)]
pub const fn int_raw(&self) -> &INT_RAW {
&self.int_raw
}
#[doc = "0x64 - state of interrupt"]
#[inline(always)]
pub const fn int_st(&self) -> &INT_ST {
&self.int_st
}
#[doc = "0x68 - clear interrupt"]
#[inline(always)]
pub const fn int_clr(&self) -> &INT_CLR {
&self.int_clr
}
#[doc = "0x6c - configure apb saradc dma"]
#[inline(always)]
pub const fn dma_conf(&self) -> &DMA_CONF {
&self.dma_conf
}
#[doc = "0x70 - configure apb saradc clock"]
#[inline(always)]
pub const fn clkm_conf(&self) -> &CLKM_CONF {
&self.clkm_conf
}
#[doc = "0x78 - get apb saradc2 sample data"]
#[inline(always)]
pub const fn apb_saradc2_data_status(&self) -> &APB_SARADC2_DATA_STATUS {
&self.apb_saradc2_data_status
}
#[doc = "0x3fc - version"]
#[inline(always)]
pub const fn ctrl_date(&self) -> &CTRL_DATE {
&self.ctrl_date
}
}
#[doc = "CTRL (rw) register accessor: configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
#[doc = "configure apb saradc controller"]
pub mod ctrl;
#[doc = "CTRL2 (rw) register accessor: configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"]
pub type CTRL2 = crate::Reg<ctrl2::CTRL2_SPEC>;
#[doc = "configure apb saradc controller"]
pub mod ctrl2;
#[doc = "FILTER_CTRL1 (rw) register accessor: configure saradc filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_ctrl1`] module"]
pub type FILTER_CTRL1 = crate::Reg<filter_ctrl1::FILTER_CTRL1_SPEC>;
#[doc = "configure saradc filter"]
pub mod filter_ctrl1;
#[doc = "FSM_WAIT (rw) register accessor: configure apb saradc fsm\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm_wait::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsm_wait::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm_wait`] module"]
pub type FSM_WAIT = crate::Reg<fsm_wait::FSM_WAIT_SPEC>;
#[doc = "configure apb saradc fsm"]
pub mod fsm_wait;
#[doc = "SAR1_STATUS (r) register accessor: saradc1 status for debug\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_status`] module"]
pub type SAR1_STATUS = crate::Reg<sar1_status::SAR1_STATUS_SPEC>;
#[doc = "saradc1 status for debug"]
pub mod sar1_status;
#[doc = "SAR2_STATUS (r) register accessor: saradc2 status for debug\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_status`] module"]
pub type SAR2_STATUS = crate::Reg<sar2_status::SAR2_STATUS_SPEC>;
#[doc = "saradc2 status for debug"]
pub mod sar2_status;
#[doc = "SAR1_PATT_TAB1 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab1`] module"]
pub type SAR1_PATT_TAB1 = crate::Reg<sar1_patt_tab1::SAR1_PATT_TAB1_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar1_patt_tab1;
#[doc = "SAR1_PATT_TAB2 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab2`] module"]
pub type SAR1_PATT_TAB2 = crate::Reg<sar1_patt_tab2::SAR1_PATT_TAB2_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar1_patt_tab2;
#[doc = "SAR1_PATT_TAB3 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab3`] module"]
pub type SAR1_PATT_TAB3 = crate::Reg<sar1_patt_tab3::SAR1_PATT_TAB3_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar1_patt_tab3;
#[doc = "SAR1_PATT_TAB4 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab4`] module"]
pub type SAR1_PATT_TAB4 = crate::Reg<sar1_patt_tab4::SAR1_PATT_TAB4_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar1_patt_tab4;
#[doc = "SAR2_PATT_TAB1 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab1`] module"]
pub type SAR2_PATT_TAB1 = crate::Reg<sar2_patt_tab1::SAR2_PATT_TAB1_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar2_patt_tab1;
#[doc = "SAR2_PATT_TAB2 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab2`] module"]
pub type SAR2_PATT_TAB2 = crate::Reg<sar2_patt_tab2::SAR2_PATT_TAB2_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar2_patt_tab2;
#[doc = "SAR2_PATT_TAB3 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab3`] module"]
pub type SAR2_PATT_TAB3 = crate::Reg<sar2_patt_tab3::SAR2_PATT_TAB3_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar2_patt_tab3;
#[doc = "SAR2_PATT_TAB4 (rw) register accessor: configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab4`] module"]
pub type SAR2_PATT_TAB4 = crate::Reg<sar2_patt_tab4::SAR2_PATT_TAB4_SPEC>;
#[doc = "configure apb saradc pattern table"]
pub mod sar2_patt_tab4;
#[doc = "ARB_CTRL (rw) register accessor: configure apb saradc arbit\n\nYou can [`read`](crate::Reg::read) this register and get [`arb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arb_ctrl`] module"]
pub type ARB_CTRL = crate::Reg<arb_ctrl::ARB_CTRL_SPEC>;
#[doc = "configure apb saradc arbit"]
pub mod arb_ctrl;
#[doc = "FILTER_CTRL0 (rw) register accessor: configure apb saradc arbit\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_ctrl0`] module"]
pub type FILTER_CTRL0 = crate::Reg<filter_ctrl0::FILTER_CTRL0_SPEC>;
#[doc = "configure apb saradc arbit"]
pub mod filter_ctrl0;
#[doc = "APB_SARADC1_DATA_STATUS (r) register accessor: get apb saradc sample data\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_saradc1_data_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_saradc1_data_status`] module"]
pub type APB_SARADC1_DATA_STATUS =
crate::Reg<apb_saradc1_data_status::APB_SARADC1_DATA_STATUS_SPEC>;
#[doc = "get apb saradc sample data"]
pub mod apb_saradc1_data_status;
#[doc = "THRES0_CTRL (rw) register accessor: configure apb saradc thres monitor\n\nYou can [`read`](crate::Reg::read) this register and get [`thres0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thres0_ctrl`] module"]
pub type THRES0_CTRL = crate::Reg<thres0_ctrl::THRES0_CTRL_SPEC>;
#[doc = "configure apb saradc thres monitor"]
pub mod thres0_ctrl;
#[doc = "THRES1_CTRL (rw) register accessor: configure apb saradc thres monitor\n\nYou can [`read`](crate::Reg::read) this register and get [`thres1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thres1_ctrl`] module"]
pub type THRES1_CTRL = crate::Reg<thres1_ctrl::THRES1_CTRL_SPEC>;
#[doc = "configure apb saradc thres monitor"]
pub mod thres1_ctrl;
#[doc = "THRES_CTRL (rw) register accessor: configure thres monitor enable\n\nYou can [`read`](crate::Reg::read) this register and get [`thres_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thres_ctrl`] module"]
pub type THRES_CTRL = crate::Reg<thres_ctrl::THRES_CTRL_SPEC>;
#[doc = "configure thres monitor enable"]
pub mod thres_ctrl;
#[doc = "INT_ENA (rw) register accessor: enable interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
#[doc = "enable interrupt"]
pub mod int_ena;
#[doc = "INT_RAW (r) register accessor: raw of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
#[doc = "raw of interrupt"]
pub mod int_raw;
#[doc = "INT_ST (r) register accessor: state of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
#[doc = "state of interrupt"]
pub mod int_st;
#[doc = "INT_CLR (w) register accessor: clear interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
#[doc = "clear interrupt"]
pub mod int_clr;
#[doc = "DMA_CONF (rw) register accessor: configure apb saradc dma\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_conf`] module"]
pub type DMA_CONF = crate::Reg<dma_conf::DMA_CONF_SPEC>;
#[doc = "configure apb saradc dma"]
pub mod dma_conf;
#[doc = "CLKM_CONF (rw) register accessor: configure apb saradc clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkm_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkm_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkm_conf`] module"]
pub type CLKM_CONF = crate::Reg<clkm_conf::CLKM_CONF_SPEC>;
#[doc = "configure apb saradc clock"]
pub mod clkm_conf;
#[doc = "APB_SARADC2_DATA_STATUS (r) register accessor: get apb saradc2 sample data\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_saradc2_data_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_saradc2_data_status`] module"]
pub type APB_SARADC2_DATA_STATUS =
crate::Reg<apb_saradc2_data_status::APB_SARADC2_DATA_STATUS_SPEC>;
#[doc = "get apb saradc2 sample data"]
pub mod apb_saradc2_data_status;
#[doc = "CTRL_DATE (rw) register accessor: version\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_date`] module"]
pub type CTRL_DATE = crate::Reg<ctrl_date::CTRL_DATE_SPEC>;
#[doc = "version"]
pub mod ctrl_date;
vendor/esp32s3/src/apb_saradc/apb_saradc1_data_status.rs
Vendored
+30
View File
@@ -0,0 +1,30 @@
#[doc = "Register `APB_SARADC1_DATA_STATUS` reader"]
pub type R = crate::R<APB_SARADC1_DATA_STATUS_SPEC>;
#[doc = "Field `SARADC1_DATA` reader - apbsaradc sample data"]
pub type SARADC1_DATA_R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:16 - apbsaradc sample data"]
#[inline(always)]
pub fn saradc1_data(&self) -> SARADC1_DATA_R {
SARADC1_DATA_R::new(self.bits & 0x0001_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC1_DATA_STATUS")
.field("saradc1_data", &self.saradc1_data())
.finish()
}
}
#[doc = "get apb saradc sample data\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_saradc1_data_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APB_SARADC1_DATA_STATUS_SPEC;
impl crate::RegisterSpec for APB_SARADC1_DATA_STATUS_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`apb_saradc1_data_status::R`](R) reader structure"]
impl crate::Readable for APB_SARADC1_DATA_STATUS_SPEC {}
#[doc = "`reset()` method sets APB_SARADC1_DATA_STATUS to value 0"]
impl crate::Resettable for APB_SARADC1_DATA_STATUS_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/apb_saradc2_data_status.rs
Vendored
+30
View File
@@ -0,0 +1,30 @@
#[doc = "Register `APB_SARADC2_DATA_STATUS` reader"]
pub type R = crate::R<APB_SARADC2_DATA_STATUS_SPEC>;
#[doc = "Field `SARADC2_DATA` reader - apb saradc2 sample data"]
pub type SARADC2_DATA_R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:16 - apb saradc2 sample data"]
#[inline(always)]
pub fn saradc2_data(&self) -> SARADC2_DATA_R {
SARADC2_DATA_R::new(self.bits & 0x0001_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC2_DATA_STATUS")
.field("saradc2_data", &self.saradc2_data())
.finish()
}
}
#[doc = "get apb saradc2 sample data\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_saradc2_data_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APB_SARADC2_DATA_STATUS_SPEC;
impl crate::RegisterSpec for APB_SARADC2_DATA_STATUS_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`apb_saradc2_data_status::R`](R) reader structure"]
impl crate::Readable for APB_SARADC2_DATA_STATUS_SPEC {}
#[doc = "`reset()` method sets APB_SARADC2_DATA_STATUS to value 0"]
impl crate::Resettable for APB_SARADC2_DATA_STATUS_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/arb_ctrl.rs
Vendored
+152
View File
@@ -0,0 +1,152 @@
#[doc = "Register `ARB_CTRL` reader"]
pub type R = crate::R<ARB_CTRL_SPEC>;
#[doc = "Register `ARB_CTRL` writer"]
pub type W = crate::W<ARB_CTRL_SPEC>;
#[doc = "Field `APB_FORCE` reader - adc2 arbiter force to enableapb controller"]
pub type APB_FORCE_R = crate::BitReader;
#[doc = "Field `APB_FORCE` writer - adc2 arbiter force to enableapb controller"]
pub type APB_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTC_FORCE` reader - adc2 arbiter force to enable rtc controller"]
pub type RTC_FORCE_R = crate::BitReader;
#[doc = "Field `RTC_FORCE` writer - adc2 arbiter force to enable rtc controller"]
pub type RTC_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WIFI_FORCE` reader - adc2 arbiter force to enable wifi controller"]
pub type WIFI_FORCE_R = crate::BitReader;
#[doc = "Field `WIFI_FORCE` writer - adc2 arbiter force to enable wifi controller"]
pub type WIFI_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GRANT_FORCE` reader - adc2 arbiter force grant"]
pub type GRANT_FORCE_R = crate::BitReader;
#[doc = "Field `GRANT_FORCE` writer - adc2 arbiter force grant"]
pub type GRANT_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_PRIORITY` reader - Set adc2 arbiterapb priority"]
pub type APB_PRIORITY_R = crate::FieldReader;
#[doc = "Field `APB_PRIORITY` writer - Set adc2 arbiterapb priority"]
pub type APB_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RTC_PRIORITY` reader - Set adc2 arbiter rtc priority"]
pub type RTC_PRIORITY_R = crate::FieldReader;
#[doc = "Field `RTC_PRIORITY` writer - Set adc2 arbiter rtc priority"]
pub type RTC_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `WIFI_PRIORITY` reader - Set adc2 arbiter wifi priority"]
pub type WIFI_PRIORITY_R = crate::FieldReader;
#[doc = "Field `WIFI_PRIORITY` writer - Set adc2 arbiter wifi priority"]
pub type WIFI_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `FIX_PRIORITY` reader - adc2 arbiter uses fixed priority"]
pub type FIX_PRIORITY_R = crate::BitReader;
#[doc = "Field `FIX_PRIORITY` writer - adc2 arbiter uses fixed priority"]
pub type FIX_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
#[inline(always)]
pub fn apb_force(&self) -> APB_FORCE_R {
APB_FORCE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"]
#[inline(always)]
pub fn rtc_force(&self) -> RTC_FORCE_R {
RTC_FORCE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"]
#[inline(always)]
pub fn wifi_force(&self) -> WIFI_FORCE_R {
WIFI_FORCE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - adc2 arbiter force grant"]
#[inline(always)]
pub fn grant_force(&self) -> GRANT_FORCE_R {
GRANT_FORCE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Set adc2 arbiterapb priority"]
#[inline(always)]
pub fn apb_priority(&self) -> APB_PRIORITY_R {
APB_PRIORITY_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"]
#[inline(always)]
pub fn rtc_priority(&self) -> RTC_PRIORITY_R {
RTC_PRIORITY_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"]
#[inline(always)]
pub fn wifi_priority(&self) -> WIFI_PRIORITY_R {
WIFI_PRIORITY_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 12 - adc2 arbiter uses fixed priority"]
#[inline(always)]
pub fn fix_priority(&self) -> FIX_PRIORITY_R {
FIX_PRIORITY_R::new(((self.bits >> 12) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ARB_CTRL")
.field("apb_force", &self.apb_force())
.field("rtc_force", &self.rtc_force())
.field("wifi_force", &self.wifi_force())
.field("grant_force", &self.grant_force())
.field("apb_priority", &self.apb_priority())
.field("rtc_priority", &self.rtc_priority())
.field("wifi_priority", &self.wifi_priority())
.field("fix_priority", &self.fix_priority())
.finish()
}
}
impl W {
#[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
#[inline(always)]
pub fn apb_force(&mut self) -> APB_FORCE_W<ARB_CTRL_SPEC> {
APB_FORCE_W::new(self, 2)
}
#[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"]
#[inline(always)]
pub fn rtc_force(&mut self) -> RTC_FORCE_W<ARB_CTRL_SPEC> {
RTC_FORCE_W::new(self, 3)
}
#[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"]
#[inline(always)]
pub fn wifi_force(&mut self) -> WIFI_FORCE_W<ARB_CTRL_SPEC> {
WIFI_FORCE_W::new(self, 4)
}
#[doc = "Bit 5 - adc2 arbiter force grant"]
#[inline(always)]
pub fn grant_force(&mut self) -> GRANT_FORCE_W<ARB_CTRL_SPEC> {
GRANT_FORCE_W::new(self, 5)
}
#[doc = "Bits 6:7 - Set adc2 arbiterapb priority"]
#[inline(always)]
pub fn apb_priority(&mut self) -> APB_PRIORITY_W<ARB_CTRL_SPEC> {
APB_PRIORITY_W::new(self, 6)
}
#[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"]
#[inline(always)]
pub fn rtc_priority(&mut self) -> RTC_PRIORITY_W<ARB_CTRL_SPEC> {
RTC_PRIORITY_W::new(self, 8)
}
#[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"]
#[inline(always)]
pub fn wifi_priority(&mut self) -> WIFI_PRIORITY_W<ARB_CTRL_SPEC> {
WIFI_PRIORITY_W::new(self, 10)
}
#[doc = "Bit 12 - adc2 arbiter uses fixed priority"]
#[inline(always)]
pub fn fix_priority(&mut self) -> FIX_PRIORITY_W<ARB_CTRL_SPEC> {
FIX_PRIORITY_W::new(self, 12)
}
}
#[doc = "configure apb saradc arbit\n\nYou can [`read`](crate::Reg::read) this register and get [`arb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ARB_CTRL_SPEC;
impl crate::RegisterSpec for ARB_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`arb_ctrl::R`](R) reader structure"]
impl crate::Readable for ARB_CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`arb_ctrl::W`](W) writer structure"]
impl crate::Writable for ARB_CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARB_CTRL to value 0x0900"]
impl crate::Resettable for ARB_CTRL_SPEC {
const RESET_VALUE: u32 = 0x0900;
}
vendor/esp32s3/src/apb_saradc/clkm_conf.rs
Vendored
+107
View File
@@ -0,0 +1,107 @@
#[doc = "Register `CLKM_CONF` reader"]
pub type R = crate::R<CLKM_CONF_SPEC>;
#[doc = "Register `CLKM_CONF` writer"]
pub type W = crate::W<CLKM_CONF_SPEC>;
#[doc = "Field `CLKM_DIV_NUM` reader - Integral clock divider value"]
pub type CLKM_DIV_NUM_R = crate::FieldReader;
#[doc = "Field `CLKM_DIV_NUM` writer - Integral clock divider value"]
pub type CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `CLKM_DIV_B` reader - Fractional clock divider numerator value"]
pub type CLKM_DIV_B_R = crate::FieldReader;
#[doc = "Field `CLKM_DIV_B` writer - Fractional clock divider numerator value"]
pub type CLKM_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `CLKM_DIV_A` reader - Fractional clock divider denominator value"]
pub type CLKM_DIV_A_R = crate::FieldReader;
#[doc = "Field `CLKM_DIV_A` writer - Fractional clock divider denominator value"]
pub type CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `CLK_EN` reader - no public"]
pub type CLK_EN_R = crate::BitReader;
#[doc = "Field `CLK_EN` writer - no public"]
pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_SEL` reader - Set this bit to enable clk_apll"]
pub type CLK_SEL_R = crate::FieldReader;
#[doc = "Field `CLK_SEL` writer - Set this bit to enable clk_apll"]
pub type CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:7 - Integral clock divider value"]
#[inline(always)]
pub fn clkm_div_num(&self) -> CLKM_DIV_NUM_R {
CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:13 - Fractional clock divider numerator value"]
#[inline(always)]
pub fn clkm_div_b(&self) -> CLKM_DIV_B_R {
CLKM_DIV_B_R::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:19 - Fractional clock divider denominator value"]
#[inline(always)]
pub fn clkm_div_a(&self) -> CLKM_DIV_A_R {
CLKM_DIV_A_R::new(((self.bits >> 14) & 0x3f) as u8)
}
#[doc = "Bit 20 - no public"]
#[inline(always)]
pub fn clk_en(&self) -> CLK_EN_R {
CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
#[inline(always)]
pub fn clk_sel(&self) -> CLK_SEL_R {
CLK_SEL_R::new(((self.bits >> 21) & 3) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CLKM_CONF")
.field("clkm_div_num", &self.clkm_div_num())
.field("clkm_div_b", &self.clkm_div_b())
.field("clkm_div_a", &self.clkm_div_a())
.field("clk_en", &self.clk_en())
.field("clk_sel", &self.clk_sel())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Integral clock divider value"]
#[inline(always)]
pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
CLKM_DIV_NUM_W::new(self, 0)
}
#[doc = "Bits 8:13 - Fractional clock divider numerator value"]
#[inline(always)]
pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
CLKM_DIV_B_W::new(self, 8)
}
#[doc = "Bits 14:19 - Fractional clock divider denominator value"]
#[inline(always)]
pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
CLKM_DIV_A_W::new(self, 14)
}
#[doc = "Bit 20 - no public"]
#[inline(always)]
pub fn clk_en(&mut self) -> CLK_EN_W<CLKM_CONF_SPEC> {
CLK_EN_W::new(self, 20)
}
#[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
#[inline(always)]
pub fn clk_sel(&mut self) -> CLK_SEL_W<CLKM_CONF_SPEC> {
CLK_SEL_W::new(self, 21)
}
}
#[doc = "configure apb saradc clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKM_CONF_SPEC;
impl crate::RegisterSpec for CLKM_CONF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`clkm_conf::R`](R) reader structure"]
impl crate::Readable for CLKM_CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`clkm_conf::W`](W) writer structure"]
impl crate::Writable for CLKM_CONF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CLKM_CONF to value 0x04"]
impl crate::Resettable for CLKM_CONF_SPEC {
const RESET_VALUE: u32 = 0x04;
}
vendor/esp32s3/src/apb_saradc/ctrl.rs
Vendored
+242
View File
@@ -0,0 +1,242 @@
#[doc = "Register `CTRL` reader"]
pub type R = crate::R<CTRL_SPEC>;
#[doc = "Register `CTRL` writer"]
pub type W = crate::W<CTRL_SPEC>;
#[doc = "Field `START_FORCE` reader - enable start saradc by sw"]
pub type START_FORCE_R = crate::BitReader;
#[doc = "Field `START_FORCE` writer - enable start saradc by sw"]
pub type START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `START` reader - start saradc by sw"]
pub type START_R = crate::BitReader;
#[doc = "Field `START` writer - start saradc by sw"]
pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WORK_MODE` reader - 0: single mode, 1: double mode, 2: alternate mode"]
pub type WORK_MODE_R = crate::FieldReader;
#[doc = "Field `WORK_MODE` writer - 0: single mode, 1: double mode, 2: alternate mode"]
pub type WORK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SAR_SEL` reader - 0: SAR1, 1: SAR2, only work for single SAR mode"]
pub type SAR_SEL_R = crate::BitReader;
#[doc = "Field `SAR_SEL` writer - 0: SAR1, 1: SAR2, only work for single SAR mode"]
pub type SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAR_CLK_GATED` reader - enable SAR CLK gate when saradc idle"]
pub type SAR_CLK_GATED_R = crate::BitReader;
#[doc = "Field `SAR_CLK_GATED` writer - enable SAR CLK gate when saradc idle"]
pub type SAR_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAR_CLK_DIV` reader - SAR clock divider"]
pub type SAR_CLK_DIV_R = crate::FieldReader;
#[doc = "Field `SAR_CLK_DIV` writer - SAR clock divider"]
pub type SAR_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SAR1_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
pub type SAR1_PATT_LEN_R = crate::FieldReader;
#[doc = "Field `SAR1_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
pub type SAR1_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `SAR2_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
pub type SAR2_PATT_LEN_R = crate::FieldReader;
#[doc = "Field `SAR2_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
pub type SAR2_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `SAR1_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC1 CTRL"]
pub type SAR1_PATT_P_CLEAR_R = crate::BitReader;
#[doc = "Field `SAR1_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC1 CTRL"]
pub type SAR1_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAR2_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC2 CTRL"]
pub type SAR2_PATT_P_CLEAR_R = crate::BitReader;
#[doc = "Field `SAR2_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC2 CTRL"]
pub type SAR2_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA_SAR_SEL` reader - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
pub type DATA_SAR_SEL_R = crate::BitReader;
#[doc = "Field `DATA_SAR_SEL` writer - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
pub type DATA_SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA_TO_I2S` reader - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
pub type DATA_TO_I2S_R = crate::BitReader;
#[doc = "Field `DATA_TO_I2S` writer - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
pub type DATA_TO_I2S_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `XPD_SAR_FORCE` reader - force option to xpd sar blocks"]
pub type XPD_SAR_FORCE_R = crate::FieldReader;
#[doc = "Field `XPD_SAR_FORCE` writer - force option to xpd sar blocks"]
pub type XPD_SAR_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `WAIT_ARB_CYCLE` reader - wait arbit signal stable after sar_done"]
pub type WAIT_ARB_CYCLE_R = crate::FieldReader;
#[doc = "Field `WAIT_ARB_CYCLE` writer - wait arbit signal stable after sar_done"]
pub type WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bit 0 - enable start saradc by sw"]
#[inline(always)]
pub fn start_force(&self) -> START_FORCE_R {
START_FORCE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - start saradc by sw"]
#[inline(always)]
pub fn start(&self) -> START_R {
START_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
#[inline(always)]
pub fn work_mode(&self) -> WORK_MODE_R {
WORK_MODE_R::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
#[inline(always)]
pub fn sar_sel(&self) -> SAR_SEL_R {
SAR_SEL_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
#[inline(always)]
pub fn sar_clk_gated(&self) -> SAR_CLK_GATED_R {
SAR_CLK_GATED_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:14 - SAR clock divider"]
#[inline(always)]
pub fn sar_clk_div(&self) -> SAR_CLK_DIV_R {
SAR_CLK_DIV_R::new(((self.bits >> 7) & 0xff) as u8)
}
#[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
#[inline(always)]
pub fn sar1_patt_len(&self) -> SAR1_PATT_LEN_R {
SAR1_PATT_LEN_R::new(((self.bits >> 15) & 0x0f) as u8)
}
#[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
#[inline(always)]
pub fn sar2_patt_len(&self) -> SAR2_PATT_LEN_R {
SAR2_PATT_LEN_R::new(((self.bits >> 19) & 0x0f) as u8)
}
#[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
#[inline(always)]
pub fn sar1_patt_p_clear(&self) -> SAR1_PATT_P_CLEAR_R {
SAR1_PATT_P_CLEAR_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
#[inline(always)]
pub fn sar2_patt_p_clear(&self) -> SAR2_PATT_P_CLEAR_R {
SAR2_PATT_P_CLEAR_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
#[inline(always)]
pub fn data_sar_sel(&self) -> DATA_SAR_SEL_R {
DATA_SAR_SEL_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
#[inline(always)]
pub fn data_to_i2s(&self) -> DATA_TO_I2S_R {
DATA_TO_I2S_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bits 27:28 - force option to xpd sar blocks"]
#[inline(always)]
pub fn xpd_sar_force(&self) -> XPD_SAR_FORCE_R {
XPD_SAR_FORCE_R::new(((self.bits >> 27) & 3) as u8)
}
#[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
#[inline(always)]
pub fn wait_arb_cycle(&self) -> WAIT_ARB_CYCLE_R {
WAIT_ARB_CYCLE_R::new(((self.bits >> 30) & 3) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CTRL")
.field("start_force", &self.start_force())
.field("start", &self.start())
.field("work_mode", &self.work_mode())
.field("sar_sel", &self.sar_sel())
.field("sar_clk_gated", &self.sar_clk_gated())
.field("sar_clk_div", &self.sar_clk_div())
.field("sar1_patt_len", &self.sar1_patt_len())
.field("sar2_patt_len", &self.sar2_patt_len())
.field("sar1_patt_p_clear", &self.sar1_patt_p_clear())
.field("sar2_patt_p_clear", &self.sar2_patt_p_clear())
.field("data_sar_sel", &self.data_sar_sel())
.field("data_to_i2s", &self.data_to_i2s())
.field("xpd_sar_force", &self.xpd_sar_force())
.field("wait_arb_cycle", &self.wait_arb_cycle())
.finish()
}
}
impl W {
#[doc = "Bit 0 - enable start saradc by sw"]
#[inline(always)]
pub fn start_force(&mut self) -> START_FORCE_W<CTRL_SPEC> {
START_FORCE_W::new(self, 0)
}
#[doc = "Bit 1 - start saradc by sw"]
#[inline(always)]
pub fn start(&mut self) -> START_W<CTRL_SPEC> {
START_W::new(self, 1)
}
#[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
#[inline(always)]
pub fn work_mode(&mut self) -> WORK_MODE_W<CTRL_SPEC> {
WORK_MODE_W::new(self, 3)
}
#[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
#[inline(always)]
pub fn sar_sel(&mut self) -> SAR_SEL_W<CTRL_SPEC> {
SAR_SEL_W::new(self, 5)
}
#[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
#[inline(always)]
pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<CTRL_SPEC> {
SAR_CLK_GATED_W::new(self, 6)
}
#[doc = "Bits 7:14 - SAR clock divider"]
#[inline(always)]
pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<CTRL_SPEC> {
SAR_CLK_DIV_W::new(self, 7)
}
#[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
#[inline(always)]
pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W<CTRL_SPEC> {
SAR1_PATT_LEN_W::new(self, 15)
}
#[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
#[inline(always)]
pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W<CTRL_SPEC> {
SAR2_PATT_LEN_W::new(self, 19)
}
#[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
#[inline(always)]
pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W<CTRL_SPEC> {
SAR1_PATT_P_CLEAR_W::new(self, 23)
}
#[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
#[inline(always)]
pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W<CTRL_SPEC> {
SAR2_PATT_P_CLEAR_W::new(self, 24)
}
#[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
#[inline(always)]
pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W<CTRL_SPEC> {
DATA_SAR_SEL_W::new(self, 25)
}
#[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
#[inline(always)]
pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W<CTRL_SPEC> {
DATA_TO_I2S_W::new(self, 26)
}
#[doc = "Bits 27:28 - force option to xpd sar blocks"]
#[inline(always)]
pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<CTRL_SPEC> {
XPD_SAR_FORCE_W::new(self, 27)
}
#[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
#[inline(always)]
pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<CTRL_SPEC> {
WAIT_ARB_CYCLE_W::new(self, 30)
}
}
#[doc = "configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRL_SPEC;
impl crate::RegisterSpec for CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
impl crate::Readable for CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate::Writable for CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTRL to value 0x407f_8240"]
impl crate::Resettable for CTRL_SPEC {
const RESET_VALUE: u32 = 0x407f_8240;
}
vendor/esp32s3/src/apb_saradc/ctrl2.rs
Vendored
+137
View File
@@ -0,0 +1,137 @@
#[doc = "Register `CTRL2` reader"]
pub type R = crate::R<CTRL2_SPEC>;
#[doc = "Register `CTRL2` writer"]
pub type W = crate::W<CTRL2_SPEC>;
#[doc = "Field `MEAS_NUM_LIMIT` reader - enable apb saradc limit the sample num"]
pub type MEAS_NUM_LIMIT_R = crate::BitReader;
#[doc = "Field `MEAS_NUM_LIMIT` writer - enable apb saradc limit the sample num"]
pub type MEAS_NUM_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MAX_MEAS_NUM` reader - max conversion number"]
pub type MAX_MEAS_NUM_R = crate::FieldReader;
#[doc = "Field `MAX_MEAS_NUM` writer - max conversion number"]
pub type MAX_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SAR1_INV` reader - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
pub type SAR1_INV_R = crate::BitReader;
#[doc = "Field `SAR1_INV` writer - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
pub type SAR1_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAR2_INV` reader - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
pub type SAR2_INV_R = crate::BitReader;
#[doc = "Field `SAR2_INV` writer - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
pub type SAR2_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIMER_SEL` reader - 1: select saradc timer 0: i2s_ws trigger"]
pub type TIMER_SEL_R = crate::BitReader;
#[doc = "Field `TIMER_SEL` writer - 1: select saradc timer 0: i2s_ws trigger"]
pub type TIMER_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIMER_TARGET` reader - to set saradc timer target"]
pub type TIMER_TARGET_R = crate::FieldReader<u16>;
#[doc = "Field `TIMER_TARGET` writer - to set saradc timer target"]
pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `TIMER_EN` reader - to enable saradc timer trigger"]
pub type TIMER_EN_R = crate::BitReader;
#[doc = "Field `TIMER_EN` writer - to enable saradc timer trigger"]
pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - enable apb saradc limit the sample num"]
#[inline(always)]
pub fn meas_num_limit(&self) -> MEAS_NUM_LIMIT_R {
MEAS_NUM_LIMIT_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:8 - max conversion number"]
#[inline(always)]
pub fn max_meas_num(&self) -> MAX_MEAS_NUM_R {
MAX_MEAS_NUM_R::new(((self.bits >> 1) & 0xff) as u8)
}
#[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
#[inline(always)]
pub fn sar1_inv(&self) -> SAR1_INV_R {
SAR1_INV_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
#[inline(always)]
pub fn sar2_inv(&self) -> SAR2_INV_R {
SAR2_INV_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
#[inline(always)]
pub fn timer_sel(&self) -> TIMER_SEL_R {
TIMER_SEL_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:23 - to set saradc timer target"]
#[inline(always)]
pub fn timer_target(&self) -> TIMER_TARGET_R {
TIMER_TARGET_R::new(((self.bits >> 12) & 0x0fff) as u16)
}
#[doc = "Bit 24 - to enable saradc timer trigger"]
#[inline(always)]
pub fn timer_en(&self) -> TIMER_EN_R {
TIMER_EN_R::new(((self.bits >> 24) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CTRL2")
.field("meas_num_limit", &self.meas_num_limit())
.field("max_meas_num", &self.max_meas_num())
.field("sar1_inv", &self.sar1_inv())
.field("sar2_inv", &self.sar2_inv())
.field("timer_sel", &self.timer_sel())
.field("timer_target", &self.timer_target())
.field("timer_en", &self.timer_en())
.finish()
}
}
impl W {
#[doc = "Bit 0 - enable apb saradc limit the sample num"]
#[inline(always)]
pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
MEAS_NUM_LIMIT_W::new(self, 0)
}
#[doc = "Bits 1:8 - max conversion number"]
#[inline(always)]
pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
MAX_MEAS_NUM_W::new(self, 1)
}
#[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
#[inline(always)]
pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
SAR1_INV_W::new(self, 9)
}
#[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
#[inline(always)]
pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
SAR2_INV_W::new(self, 10)
}
#[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
#[inline(always)]
pub fn timer_sel(&mut self) -> TIMER_SEL_W<CTRL2_SPEC> {
TIMER_SEL_W::new(self, 11)
}
#[doc = "Bits 12:23 - to set saradc timer target"]
#[inline(always)]
pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
TIMER_TARGET_W::new(self, 12)
}
#[doc = "Bit 24 - to enable saradc timer trigger"]
#[inline(always)]
pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
TIMER_EN_W::new(self, 24)
}
}
#[doc = "configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRL2_SPEC;
impl crate::RegisterSpec for CTRL2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
impl crate::Readable for CTRL2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
impl crate::Writable for CTRL2_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTRL2 to value 0xa1fe"]
impl crate::Resettable for CTRL2_SPEC {
const RESET_VALUE: u32 = 0xa1fe;
}
vendor/esp32s3/src/apb_saradc/ctrl_date.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `CTRL_DATE` reader"]
pub type R = crate::R<CTRL_DATE_SPEC>;
#[doc = "Register `CTRL_DATE` writer"]
pub type W = crate::W<CTRL_DATE_SPEC>;
#[doc = "Field `DATE` reader - version"]
pub type DATE_R = crate::FieldReader<u32>;
#[doc = "Field `DATE` writer - version"]
pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - version"]
#[inline(always)]
pub fn date(&self) -> DATE_R {
DATE_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CTRL_DATE")
.field("date", &self.date())
.finish()
}
}
impl W {
#[doc = "Bits 0:31 - version"]
#[inline(always)]
pub fn date(&mut self) -> DATE_W<CTRL_DATE_SPEC> {
DATE_W::new(self, 0)
}
}
#[doc = "version\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRL_DATE_SPEC;
impl crate::RegisterSpec for CTRL_DATE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl_date::R`](R) reader structure"]
impl crate::Readable for CTRL_DATE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ctrl_date::W`](W) writer structure"]
impl crate::Writable for CTRL_DATE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTRL_DATE to value 0x0210_1180"]
impl crate::Resettable for CTRL_DATE_SPEC {
const RESET_VALUE: u32 = 0x0210_1180;
}
vendor/esp32s3/src/apb_saradc/dma_conf.rs
Vendored
+77
View File
@@ -0,0 +1,77 @@
#[doc = "Register `DMA_CONF` reader"]
pub type R = crate::R<DMA_CONF_SPEC>;
#[doc = "Register `DMA_CONF` writer"]
pub type W = crate::W<DMA_CONF_SPEC>;
#[doc = "Field `ADC_EOF_NUM` reader - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
pub type ADC_EOF_NUM_R = crate::FieldReader<u16>;
#[doc = "Field `ADC_EOF_NUM` writer - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
pub type ADC_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `ADC_RESET_FSM` reader - reset_apb_adc_state"]
pub type ADC_RESET_FSM_R = crate::BitReader;
#[doc = "Field `ADC_RESET_FSM` writer - reset_apb_adc_state"]
pub type ADC_RESET_FSM_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_TRANS` reader - enable apb_adc use spi_dma"]
pub type ADC_TRANS_R = crate::BitReader;
#[doc = "Field `ADC_TRANS` writer - enable apb_adc use spi_dma"]
pub type ADC_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
#[inline(always)]
pub fn adc_eof_num(&self) -> ADC_EOF_NUM_R {
ADC_EOF_NUM_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 30 - reset_apb_adc_state"]
#[inline(always)]
pub fn adc_reset_fsm(&self) -> ADC_RESET_FSM_R {
ADC_RESET_FSM_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - enable apb_adc use spi_dma"]
#[inline(always)]
pub fn adc_trans(&self) -> ADC_TRANS_R {
ADC_TRANS_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA_CONF")
.field("adc_eof_num", &self.adc_eof_num())
.field("adc_reset_fsm", &self.adc_reset_fsm())
.field("adc_trans", &self.adc_trans())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
#[inline(always)]
pub fn adc_eof_num(&mut self) -> ADC_EOF_NUM_W<DMA_CONF_SPEC> {
ADC_EOF_NUM_W::new(self, 0)
}
#[doc = "Bit 30 - reset_apb_adc_state"]
#[inline(always)]
pub fn adc_reset_fsm(&mut self) -> ADC_RESET_FSM_W<DMA_CONF_SPEC> {
ADC_RESET_FSM_W::new(self, 30)
}
#[doc = "Bit 31 - enable apb_adc use spi_dma"]
#[inline(always)]
pub fn adc_trans(&mut self) -> ADC_TRANS_W<DMA_CONF_SPEC> {
ADC_TRANS_W::new(self, 31)
}
}
#[doc = "configure apb saradc dma\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMA_CONF_SPEC;
impl crate::RegisterSpec for DMA_CONF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma_conf::R`](R) reader structure"]
impl crate::Readable for DMA_CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`dma_conf::W`](W) writer structure"]
impl crate::Writable for DMA_CONF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DMA_CONF to value 0xff"]
impl crate::Resettable for DMA_CONF_SPEC {
const RESET_VALUE: u32 = 0xff;
}
vendor/esp32s3/src/apb_saradc/filter_ctrl0.rs
Vendored
+77
View File
@@ -0,0 +1,77 @@
#[doc = "Register `FILTER_CTRL0` reader"]
pub type R = crate::R<FILTER_CTRL0_SPEC>;
#[doc = "Register `FILTER_CTRL0` writer"]
pub type W = crate::W<FILTER_CTRL0_SPEC>;
#[doc = "Field `FILTER_CHANNEL1` reader - configure the filter1 channel"]
pub type FILTER_CHANNEL1_R = crate::FieldReader;
#[doc = "Field `FILTER_CHANNEL1` writer - configure the filter1 channel"]
pub type FILTER_CHANNEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `FILTER_CHANNEL0` reader - configure the filter0 channel"]
pub type FILTER_CHANNEL0_R = crate::FieldReader;
#[doc = "Field `FILTER_CHANNEL0` writer - configure the filter0 channel"]
pub type FILTER_CHANNEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `FILTER_RESET` reader - enable apb_adc1_filter"]
pub type FILTER_RESET_R = crate::BitReader;
#[doc = "Field `FILTER_RESET` writer - enable apb_adc1_filter"]
pub type FILTER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 14:18 - configure the filter1 channel"]
#[inline(always)]
pub fn filter_channel1(&self) -> FILTER_CHANNEL1_R {
FILTER_CHANNEL1_R::new(((self.bits >> 14) & 0x1f) as u8)
}
#[doc = "Bits 19:23 - configure the filter0 channel"]
#[inline(always)]
pub fn filter_channel0(&self) -> FILTER_CHANNEL0_R {
FILTER_CHANNEL0_R::new(((self.bits >> 19) & 0x1f) as u8)
}
#[doc = "Bit 31 - enable apb_adc1_filter"]
#[inline(always)]
pub fn filter_reset(&self) -> FILTER_RESET_R {
FILTER_RESET_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FILTER_CTRL0")
.field("filter_channel1", &self.filter_channel1())
.field("filter_channel0", &self.filter_channel0())
.field("filter_reset", &self.filter_reset())
.finish()
}
}
impl W {
#[doc = "Bits 14:18 - configure the filter1 channel"]
#[inline(always)]
pub fn filter_channel1(&mut self) -> FILTER_CHANNEL1_W<FILTER_CTRL0_SPEC> {
FILTER_CHANNEL1_W::new(self, 14)
}
#[doc = "Bits 19:23 - configure the filter0 channel"]
#[inline(always)]
pub fn filter_channel0(&mut self) -> FILTER_CHANNEL0_W<FILTER_CTRL0_SPEC> {
FILTER_CHANNEL0_W::new(self, 19)
}
#[doc = "Bit 31 - enable apb_adc1_filter"]
#[inline(always)]
pub fn filter_reset(&mut self) -> FILTER_RESET_W<FILTER_CTRL0_SPEC> {
FILTER_RESET_W::new(self, 31)
}
}
#[doc = "configure apb saradc arbit\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FILTER_CTRL0_SPEC;
impl crate::RegisterSpec for FILTER_CTRL0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`filter_ctrl0::R`](R) reader structure"]
impl crate::Readable for FILTER_CTRL0_SPEC {}
#[doc = "`write(|w| ..)` method takes [`filter_ctrl0::W`](W) writer structure"]
impl crate::Writable for FILTER_CTRL0_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FILTER_CTRL0 to value 0x006b_4000"]
impl crate::Resettable for FILTER_CTRL0_SPEC {
const RESET_VALUE: u32 = 0x006b_4000;
}
vendor/esp32s3/src/apb_saradc/filter_ctrl1.rs
Vendored
+62
View File
@@ -0,0 +1,62 @@
#[doc = "Register `FILTER_CTRL1` reader"]
pub type R = crate::R<FILTER_CTRL1_SPEC>;
#[doc = "Register `FILTER_CTRL1` writer"]
pub type W = crate::W<FILTER_CTRL1_SPEC>;
#[doc = "Field `FILTER_FACTOR1` reader - apb saradc factor1"]
pub type FILTER_FACTOR1_R = crate::FieldReader;
#[doc = "Field `FILTER_FACTOR1` writer - apb saradc factor1"]
pub type FILTER_FACTOR1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `FILTER_FACTOR0` reader - apb saradc factor0"]
pub type FILTER_FACTOR0_R = crate::FieldReader;
#[doc = "Field `FILTER_FACTOR0` writer - apb saradc factor0"]
pub type FILTER_FACTOR0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bits 26:28 - apb saradc factor1"]
#[inline(always)]
pub fn filter_factor1(&self) -> FILTER_FACTOR1_R {
FILTER_FACTOR1_R::new(((self.bits >> 26) & 7) as u8)
}
#[doc = "Bits 29:31 - apb saradc factor0"]
#[inline(always)]
pub fn filter_factor0(&self) -> FILTER_FACTOR0_R {
FILTER_FACTOR0_R::new(((self.bits >> 29) & 7) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FILTER_CTRL1")
.field("filter_factor1", &self.filter_factor1())
.field("filter_factor0", &self.filter_factor0())
.finish()
}
}
impl W {
#[doc = "Bits 26:28 - apb saradc factor1"]
#[inline(always)]
pub fn filter_factor1(&mut self) -> FILTER_FACTOR1_W<FILTER_CTRL1_SPEC> {
FILTER_FACTOR1_W::new(self, 26)
}
#[doc = "Bits 29:31 - apb saradc factor0"]
#[inline(always)]
pub fn filter_factor0(&mut self) -> FILTER_FACTOR0_W<FILTER_CTRL1_SPEC> {
FILTER_FACTOR0_W::new(self, 29)
}
}
#[doc = "configure saradc filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FILTER_CTRL1_SPEC;
impl crate::RegisterSpec for FILTER_CTRL1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`filter_ctrl1::R`](R) reader structure"]
impl crate::Readable for FILTER_CTRL1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`filter_ctrl1::W`](W) writer structure"]
impl crate::Writable for FILTER_CTRL1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FILTER_CTRL1 to value 0"]
impl crate::Resettable for FILTER_CTRL1_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/fsm_wait.rs
Vendored
+77
View File
@@ -0,0 +1,77 @@
#[doc = "Register `FSM_WAIT` reader"]
pub type R = crate::R<FSM_WAIT_SPEC>;
#[doc = "Register `FSM_WAIT` writer"]
pub type W = crate::W<FSM_WAIT_SPEC>;
#[doc = "Field `XPD_WAIT` reader - the cycle which saradc controller in xpd state"]
pub type XPD_WAIT_R = crate::FieldReader;
#[doc = "Field `XPD_WAIT` writer - the cycle which saradc controller in xpd state"]
pub type XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSTB_WAIT` reader - the cycle which saradc controller in rst state"]
pub type RSTB_WAIT_R = crate::FieldReader;
#[doc = "Field `RSTB_WAIT` writer - the cycle which saradc controller in rst state"]
pub type RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `STANDBY_WAIT` reader - the cycle which saradc controller in standby state"]
pub type STANDBY_WAIT_R = crate::FieldReader;
#[doc = "Field `STANDBY_WAIT` writer - the cycle which saradc controller in standby state"]
pub type STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
#[inline(always)]
pub fn xpd_wait(&self) -> XPD_WAIT_R {
XPD_WAIT_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
#[inline(always)]
pub fn rstb_wait(&self) -> RSTB_WAIT_R {
RSTB_WAIT_R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
#[inline(always)]
pub fn standby_wait(&self) -> STANDBY_WAIT_R {
STANDBY_WAIT_R::new(((self.bits >> 16) & 0xff) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FSM_WAIT")
.field("xpd_wait", &self.xpd_wait())
.field("rstb_wait", &self.rstb_wait())
.field("standby_wait", &self.standby_wait())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
#[inline(always)]
pub fn xpd_wait(&mut self) -> XPD_WAIT_W<FSM_WAIT_SPEC> {
XPD_WAIT_W::new(self, 0)
}
#[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
#[inline(always)]
pub fn rstb_wait(&mut self) -> RSTB_WAIT_W<FSM_WAIT_SPEC> {
RSTB_WAIT_W::new(self, 8)
}
#[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
#[inline(always)]
pub fn standby_wait(&mut self) -> STANDBY_WAIT_W<FSM_WAIT_SPEC> {
STANDBY_WAIT_W::new(self, 16)
}
}
#[doc = "configure apb saradc fsm\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm_wait::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsm_wait::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSM_WAIT_SPEC;
impl crate::RegisterSpec for FSM_WAIT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`fsm_wait::R`](R) reader structure"]
impl crate::Readable for FSM_WAIT_SPEC {}
#[doc = "`write(|w| ..)` method takes [`fsm_wait::W`](W) writer structure"]
impl crate::Writable for FSM_WAIT_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FSM_WAIT to value 0x00ff_0808"]
impl crate::Resettable for FSM_WAIT_SPEC {
const RESET_VALUE: u32 = 0x00ff_0808;
}
vendor/esp32s3/src/apb_saradc/int_clr.rs
Vendored
+67
View File
@@ -0,0 +1,67 @@
#[doc = "Register `INT_CLR` writer"]
pub type W = crate::W<INT_CLR_SPEC>;
#[doc = "Field `THRES1_LOW` writer - interrupt of thres1 low"]
pub type THRES1_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `THRES0_LOW` writer - interrupt of thres0 low"]
pub type THRES0_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `THRES1_HIGH` writer - interrupt of thres1 high"]
pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `THRES0_HIGH` writer - interrupt of thres0 high"]
pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `ADC2_DONE` writer - interrupt of sar2 done"]
pub type ADC2_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `ADC1_DONE` writer - interrupt of sar1 done"]
pub type ADC1_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
#[doc = "Bit 26 - interrupt of thres1 low"]
#[inline(always)]
pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_CLR_SPEC> {
THRES1_LOW_W::new(self, 26)
}
#[doc = "Bit 27 - interrupt of thres0 low"]
#[inline(always)]
pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_CLR_SPEC> {
THRES0_LOW_W::new(self, 27)
}
#[doc = "Bit 28 - interrupt of thres1 high"]
#[inline(always)]
pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_CLR_SPEC> {
THRES1_HIGH_W::new(self, 28)
}
#[doc = "Bit 29 - interrupt of thres0 high"]
#[inline(always)]
pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_CLR_SPEC> {
THRES0_HIGH_W::new(self, 29)
}
#[doc = "Bit 30 - interrupt of sar2 done"]
#[inline(always)]
pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_CLR_SPEC> {
ADC2_DONE_W::new(self, 30)
}
#[doc = "Bit 31 - interrupt of sar1 done"]
#[inline(always)]
pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_CLR_SPEC> {
ADC1_DONE_W::new(self, 31)
}
}
#[doc = "clear interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_CLR_SPEC;
impl crate::RegisterSpec for INT_CLR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
impl crate::Writable for INT_CLR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xfc00_0000;
}
#[doc = "`reset()` method sets INT_CLR to value 0"]
impl crate::Resettable for INT_CLR_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/int_ena.rs
Vendored
+122
View File
@@ -0,0 +1,122 @@
#[doc = "Register `INT_ENA` reader"]
pub type R = crate::R<INT_ENA_SPEC>;
#[doc = "Register `INT_ENA` writer"]
pub type W = crate::W<INT_ENA_SPEC>;
#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
pub type THRES1_LOW_R = crate::BitReader;
#[doc = "Field `THRES1_LOW` writer - interrupt of thres1 low"]
pub type THRES1_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
pub type THRES0_LOW_R = crate::BitReader;
#[doc = "Field `THRES0_LOW` writer - interrupt of thres0 low"]
pub type THRES0_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
pub type THRES1_HIGH_R = crate::BitReader;
#[doc = "Field `THRES1_HIGH` writer - interrupt of thres1 high"]
pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
pub type THRES0_HIGH_R = crate::BitReader;
#[doc = "Field `THRES0_HIGH` writer - interrupt of thres0 high"]
pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
pub type ADC2_DONE_R = crate::BitReader;
#[doc = "Field `ADC2_DONE` writer - interrupt of sar2 done"]
pub type ADC2_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
pub type ADC1_DONE_R = crate::BitReader;
#[doc = "Field `ADC1_DONE` writer - interrupt of sar1 done"]
pub type ADC1_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 26 - interrupt of thres1 low"]
#[inline(always)]
pub fn thres1_low(&self) -> THRES1_LOW_R {
THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - interrupt of thres0 low"]
#[inline(always)]
pub fn thres0_low(&self) -> THRES0_LOW_R {
THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - interrupt of thres1 high"]
#[inline(always)]
pub fn thres1_high(&self) -> THRES1_HIGH_R {
THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - interrupt of thres0 high"]
#[inline(always)]
pub fn thres0_high(&self) -> THRES0_HIGH_R {
THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - interrupt of sar2 done"]
#[inline(always)]
pub fn adc2_done(&self) -> ADC2_DONE_R {
ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - interrupt of sar1 done"]
#[inline(always)]
pub fn adc1_done(&self) -> ADC1_DONE_R {
ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_ENA")
.field("thres1_low", &self.thres1_low())
.field("thres0_low", &self.thres0_low())
.field("thres1_high", &self.thres1_high())
.field("thres0_high", &self.thres0_high())
.field("adc2_done", &self.adc2_done())
.field("adc1_done", &self.adc1_done())
.finish()
}
}
impl W {
#[doc = "Bit 26 - interrupt of thres1 low"]
#[inline(always)]
pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_ENA_SPEC> {
THRES1_LOW_W::new(self, 26)
}
#[doc = "Bit 27 - interrupt of thres0 low"]
#[inline(always)]
pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_ENA_SPEC> {
THRES0_LOW_W::new(self, 27)
}
#[doc = "Bit 28 - interrupt of thres1 high"]
#[inline(always)]
pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_ENA_SPEC> {
THRES1_HIGH_W::new(self, 28)
}
#[doc = "Bit 29 - interrupt of thres0 high"]
#[inline(always)]
pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_ENA_SPEC> {
THRES0_HIGH_W::new(self, 29)
}
#[doc = "Bit 30 - interrupt of sar2 done"]
#[inline(always)]
pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_ENA_SPEC> {
ADC2_DONE_W::new(self, 30)
}
#[doc = "Bit 31 - interrupt of sar1 done"]
#[inline(always)]
pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_ENA_SPEC> {
ADC1_DONE_W::new(self, 31)
}
}
#[doc = "enable interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_ENA_SPEC;
impl crate::RegisterSpec for INT_ENA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
impl crate::Readable for INT_ENA_SPEC {}
#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
impl crate::Writable for INT_ENA_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_ENA to value 0"]
impl crate::Resettable for INT_ENA_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/int_raw.rs
Vendored
+70
View File
@@ -0,0 +1,70 @@
#[doc = "Register `INT_RAW` reader"]
pub type R = crate::R<INT_RAW_SPEC>;
#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
pub type THRES1_LOW_R = crate::BitReader;
#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
pub type THRES0_LOW_R = crate::BitReader;
#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
pub type THRES1_HIGH_R = crate::BitReader;
#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
pub type THRES0_HIGH_R = crate::BitReader;
#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
pub type ADC2_DONE_R = crate::BitReader;
#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
pub type ADC1_DONE_R = crate::BitReader;
impl R {
#[doc = "Bit 26 - interrupt of thres1 low"]
#[inline(always)]
pub fn thres1_low(&self) -> THRES1_LOW_R {
THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - interrupt of thres0 low"]
#[inline(always)]
pub fn thres0_low(&self) -> THRES0_LOW_R {
THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - interrupt of thres1 high"]
#[inline(always)]
pub fn thres1_high(&self) -> THRES1_HIGH_R {
THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - interrupt of thres0 high"]
#[inline(always)]
pub fn thres0_high(&self) -> THRES0_HIGH_R {
THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - interrupt of sar2 done"]
#[inline(always)]
pub fn adc2_done(&self) -> ADC2_DONE_R {
ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - interrupt of sar1 done"]
#[inline(always)]
pub fn adc1_done(&self) -> ADC1_DONE_R {
ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_RAW")
.field("thres1_low", &self.thres1_low())
.field("thres0_low", &self.thres0_low())
.field("thres1_high", &self.thres1_high())
.field("thres0_high", &self.thres0_high())
.field("adc2_done", &self.adc2_done())
.field("adc1_done", &self.adc1_done())
.finish()
}
}
#[doc = "raw of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_RAW_SPEC;
impl crate::RegisterSpec for INT_RAW_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
impl crate::Readable for INT_RAW_SPEC {}
#[doc = "`reset()` method sets INT_RAW to value 0"]
impl crate::Resettable for INT_RAW_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/int_st.rs
Vendored
+70
View File
@@ -0,0 +1,70 @@
#[doc = "Register `INT_ST` reader"]
pub type R = crate::R<INT_ST_SPEC>;
#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
pub type THRES1_LOW_R = crate::BitReader;
#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
pub type THRES0_LOW_R = crate::BitReader;
#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
pub type THRES1_HIGH_R = crate::BitReader;
#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
pub type THRES0_HIGH_R = crate::BitReader;
#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
pub type ADC2_DONE_R = crate::BitReader;
#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
pub type ADC1_DONE_R = crate::BitReader;
impl R {
#[doc = "Bit 26 - interrupt of thres1 low"]
#[inline(always)]
pub fn thres1_low(&self) -> THRES1_LOW_R {
THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - interrupt of thres0 low"]
#[inline(always)]
pub fn thres0_low(&self) -> THRES0_LOW_R {
THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - interrupt of thres1 high"]
#[inline(always)]
pub fn thres1_high(&self) -> THRES1_HIGH_R {
THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - interrupt of thres0 high"]
#[inline(always)]
pub fn thres0_high(&self) -> THRES0_HIGH_R {
THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - interrupt of sar2 done"]
#[inline(always)]
pub fn adc2_done(&self) -> ADC2_DONE_R {
ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - interrupt of sar1 done"]
#[inline(always)]
pub fn adc1_done(&self) -> ADC1_DONE_R {
ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_ST")
.field("thres1_low", &self.thres1_low())
.field("thres0_low", &self.thres0_low())
.field("thres1_high", &self.thres1_high())
.field("thres0_high", &self.thres0_high())
.field("adc2_done", &self.adc2_done())
.field("adc1_done", &self.adc1_done())
.finish()
}
}
#[doc = "state of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_ST_SPEC;
impl crate::RegisterSpec for INT_ST_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
impl crate::Readable for INT_ST_SPEC {}
#[doc = "`reset()` method sets INT_ST to value 0"]
impl crate::Resettable for INT_ST_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SAR1_PATT_TAB1` reader"]
pub type R = crate::R<SAR1_PATT_TAB1_SPEC>;
#[doc = "Register `SAR1_PATT_TAB1` writer"]
pub type W = crate::W<SAR1_PATT_TAB1_SPEC>;
#[doc = "Field `SAR1_PATT_TAB1` reader - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB1_R = crate::FieldReader<u32>;
#[doc = "Field `SAR1_PATT_TAB1` writer - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab1(&self) -> SAR1_PATT_TAB1_R {
SAR1_PATT_TAB1_R::new(self.bits & 0x00ff_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAR1_PATT_TAB1")
.field("sar1_patt_tab1", &self.sar1_patt_tab1())
.finish()
}
}
impl W {
#[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab1(&mut self) -> SAR1_PATT_TAB1_W<SAR1_PATT_TAB1_SPEC> {
SAR1_PATT_TAB1_W::new(self, 0)
}
}
#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SAR1_PATT_TAB1_SPEC;
impl crate::RegisterSpec for SAR1_PATT_TAB1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar1_patt_tab1::R`](R) reader structure"]
impl crate::Readable for SAR1_PATT_TAB1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab1::W`](W) writer structure"]
impl crate::Writable for SAR1_PATT_TAB1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR1_PATT_TAB1 to value 0"]
impl crate::Resettable for SAR1_PATT_TAB1_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SAR1_PATT_TAB2` reader"]
pub type R = crate::R<SAR1_PATT_TAB2_SPEC>;
#[doc = "Register `SAR1_PATT_TAB2` writer"]
pub type W = crate::W<SAR1_PATT_TAB2_SPEC>;
#[doc = "Field `SAR1_PATT_TAB2` reader - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB2_R = crate::FieldReader<u32>;
#[doc = "Field `SAR1_PATT_TAB2` writer - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab2(&self) -> SAR1_PATT_TAB2_R {
SAR1_PATT_TAB2_R::new(self.bits & 0x00ff_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAR1_PATT_TAB2")
.field("sar1_patt_tab2", &self.sar1_patt_tab2())
.finish()
}
}
impl W {
#[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab2(&mut self) -> SAR1_PATT_TAB2_W<SAR1_PATT_TAB2_SPEC> {
SAR1_PATT_TAB2_W::new(self, 0)
}
}
#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SAR1_PATT_TAB2_SPEC;
impl crate::RegisterSpec for SAR1_PATT_TAB2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar1_patt_tab2::R`](R) reader structure"]
impl crate::Readable for SAR1_PATT_TAB2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab2::W`](W) writer structure"]
impl crate::Writable for SAR1_PATT_TAB2_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR1_PATT_TAB2 to value 0"]
impl crate::Resettable for SAR1_PATT_TAB2_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SAR1_PATT_TAB3` reader"]
pub type R = crate::R<SAR1_PATT_TAB3_SPEC>;
#[doc = "Register `SAR1_PATT_TAB3` writer"]
pub type W = crate::W<SAR1_PATT_TAB3_SPEC>;
#[doc = "Field `SAR1_PATT_TAB3` reader - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB3_R = crate::FieldReader<u32>;
#[doc = "Field `SAR1_PATT_TAB3` writer - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab3(&self) -> SAR1_PATT_TAB3_R {
SAR1_PATT_TAB3_R::new(self.bits & 0x00ff_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAR1_PATT_TAB3")
.field("sar1_patt_tab3", &self.sar1_patt_tab3())
.finish()
}
}
impl W {
#[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab3(&mut self) -> SAR1_PATT_TAB3_W<SAR1_PATT_TAB3_SPEC> {
SAR1_PATT_TAB3_W::new(self, 0)
}
}
#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SAR1_PATT_TAB3_SPEC;
impl crate::RegisterSpec for SAR1_PATT_TAB3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar1_patt_tab3::R`](R) reader structure"]
impl crate::Readable for SAR1_PATT_TAB3_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab3::W`](W) writer structure"]
impl crate::Writable for SAR1_PATT_TAB3_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR1_PATT_TAB3 to value 0"]
impl crate::Resettable for SAR1_PATT_TAB3_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
Vendored
+47
View File
@@ -0,0 +1,47 @@
#[doc = "Register `SAR1_PATT_TAB4` reader"]
pub type R = crate::R<SAR1_PATT_TAB4_SPEC>;
#[doc = "Register `SAR1_PATT_TAB4` writer"]
pub type W = crate::W<SAR1_PATT_TAB4_SPEC>;
#[doc = "Field `SAR1_PATT_TAB4` reader - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB4_R = crate::FieldReader<u32>;
#[doc = "Field `SAR1_PATT_TAB4` writer - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
pub type SAR1_PATT_TAB4_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab4(&self) -> SAR1_PATT_TAB4_R {
SAR1_PATT_TAB4_R::new(self.bits & 0x00ff_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAR1_PATT_TAB4")
.field("sar1_patt_tab4", &self.sar1_patt_tab4())
.finish()
}
}
impl W {
#[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
#[inline(always)]
pub fn sar1_patt_tab4(&mut self) -> SAR1_PATT_TAB4_W<SAR1_PATT_TAB4_SPEC> {
SAR1_PATT_TAB4_W::new(self, 0)
}
}
#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SAR1_PATT_TAB4_SPEC;
impl crate::RegisterSpec for SAR1_PATT_TAB4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar1_patt_tab4::R`](R) reader structure"]
impl crate::Readable for SAR1_PATT_TAB4_SPEC {}
#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab4::W`](W) writer structure"]
impl crate::Writable for SAR1_PATT_TAB4_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR1_PATT_TAB4 to value 0"]
impl crate::Resettable for SAR1_PATT_TAB4_SPEC {
const RESET_VALUE: u32 = 0;
}
Loaded 100 of 17624 files, more files were not shown because too many files have changed in this diff. Show more