feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/aes/aad_block_num.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `AAD_BLOCK_NUM` reader"]
+pub type R = crate::R<AAD_BLOCK_NUM_SPEC>;
+#[doc = "Register `AAD_BLOCK_NUM` writer"]
+pub type W = crate::W<AAD_BLOCK_NUM_SPEC>;
+#[doc = "Field `AAD_BLOCK_NUM` reader - Those bits stores the number of AAD block."]
+pub type AAD_BLOCK_NUM_R = crate::FieldReader<u32>;
+#[doc = "Field `AAD_BLOCK_NUM` writer - Those bits stores the number of AAD block."]
+pub type AAD_BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
+    #[inline(always)]
+    pub fn aad_block_num(&self) -> AAD_BLOCK_NUM_R {
+        AAD_BLOCK_NUM_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AAD_BLOCK_NUM")
+            .field("aad_block_num", &self.aad_block_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
+    #[inline(always)]
+    pub fn aad_block_num(&mut self) -> AAD_BLOCK_NUM_W<AAD_BLOCK_NUM_SPEC> {
+        AAD_BLOCK_NUM_W::new(self, 0)
+    }
+}
+#[doc = "Additional Authential Data block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`aad_block_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aad_block_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AAD_BLOCK_NUM_SPEC;
+impl crate::RegisterSpec for AAD_BLOCK_NUM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`aad_block_num::R`](R) reader structure"]
+impl crate::Readable for AAD_BLOCK_NUM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`aad_block_num::W`](W) writer structure"]
+impl crate::Writable for AAD_BLOCK_NUM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets AAD_BLOCK_NUM to value 0"]
+impl crate::Resettable for AAD_BLOCK_NUM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/block_mode.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `BLOCK_MODE` reader"]
+pub type R = crate::R<BLOCK_MODE_SPEC>;
+#[doc = "Register `BLOCK_MODE` writer"]
+pub type W = crate::W<BLOCK_MODE_SPEC>;
+#[doc = "Field `BLOCK_MODE` reader - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
+pub type BLOCK_MODE_R = crate::FieldReader;
+#[doc = "Field `BLOCK_MODE` writer - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
+pub type BLOCK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:2 - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
+    #[inline(always)]
+    pub fn block_mode(&self) -> BLOCK_MODE_R {
+        BLOCK_MODE_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BLOCK_MODE")
+            .field("block_mode", &self.block_mode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
+    #[inline(always)]
+    pub fn block_mode(&mut self) -> BLOCK_MODE_W<BLOCK_MODE_SPEC> {
+        BLOCK_MODE_W::new(self, 0)
+    }
+}
+#[doc = "AES cipher block mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BLOCK_MODE_SPEC;
+impl crate::RegisterSpec for BLOCK_MODE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`block_mode::R`](R) reader structure"]
+impl crate::Readable for BLOCK_MODE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`block_mode::W`](W) writer structure"]
+impl crate::Writable for BLOCK_MODE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BLOCK_MODE to value 0"]
+impl crate::Resettable for BLOCK_MODE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/block_num.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `BLOCK_NUM` reader"]
+pub type R = crate::R<BLOCK_NUM_SPEC>;
+#[doc = "Register `BLOCK_NUM` writer"]
+pub type W = crate::W<BLOCK_NUM_SPEC>;
+#[doc = "Field `BLOCK_NUM` reader - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
+pub type BLOCK_NUM_R = crate::FieldReader<u32>;
+#[doc = "Field `BLOCK_NUM` writer - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
+pub type BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
+    #[inline(always)]
+    pub fn block_num(&self) -> BLOCK_NUM_R {
+        BLOCK_NUM_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BLOCK_NUM")
+            .field("block_num", &self.block_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
+    #[inline(always)]
+    pub fn block_num(&mut self) -> BLOCK_NUM_W<BLOCK_NUM_SPEC> {
+        BLOCK_NUM_W::new(self, 0)
+    }
+}
+#[doc = "AES block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BLOCK_NUM_SPEC;
+impl crate::RegisterSpec for BLOCK_NUM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`block_num::R`](R) reader structure"]
+impl crate::Readable for BLOCK_NUM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`block_num::W`](W) writer structure"]
+impl crate::Writable for BLOCK_NUM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BLOCK_NUM to value 0"]
+impl crate::Resettable for BLOCK_NUM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/continue_.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `CONTINUE` writer"]
+pub type W = crate::W<CONTINUE_SPEC>;
+#[doc = "Field `CONTINUE` writer - Set this bit to 1 to continue GCM operation."]
+pub type CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to 1 to continue GCM operation."]
+    #[inline(always)]
+    pub fn continue_(&mut self) -> CONTINUE_W<CONTINUE_SPEC> {
+        CONTINUE_W::new(self, 0)
+    }
+}
+#[doc = "AES continue register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`continue_::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONTINUE_SPEC;
+impl crate::RegisterSpec for CONTINUE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`continue_::W`](W) writer structure"]
+impl crate::Writable for CONTINUE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONTINUE to value 0"]
+impl crate::Resettable for CONTINUE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - This bits stores the version information of AES."]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - This bits stores the version information of AES."]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
+impl R {
+    #[doc = "Bits 0:29 - This bits stores the version information of AES."]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x3fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:29 - This bits stores the version information of AES."]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "AES version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x2019_1210"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x2019_1210;
+}

vendor/esp32s3/src/aes/dma_enable.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DMA_ENABLE` reader"]
+pub type R = crate::R<DMA_ENABLE_SPEC>;
+#[doc = "Register `DMA_ENABLE` writer"]
+pub type W = crate::W<DMA_ENABLE_SPEC>;
+#[doc = "Field `DMA_ENABLE` reader - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
+pub type DMA_ENABLE_R = crate::BitReader;
+#[doc = "Field `DMA_ENABLE` writer - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
+pub type DMA_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
+    #[inline(always)]
+    pub fn dma_enable(&self) -> DMA_ENABLE_R {
+        DMA_ENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DMA_ENABLE")
+            .field("dma_enable", &self.dma_enable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
+    #[inline(always)]
+    pub fn dma_enable(&mut self) -> DMA_ENABLE_W<DMA_ENABLE_SPEC> {
+        DMA_ENABLE_W::new(self, 0)
+    }
+}
+#[doc = "AES accelerator working mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DMA_ENABLE_SPEC;
+impl crate::RegisterSpec for DMA_ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_enable::R`](R) reader structure"]
+impl crate::Readable for DMA_ENABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dma_enable::W`](W) writer structure"]
+impl crate::Writable for DMA_ENABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_ENABLE to value 0"]
+impl crate::Resettable for DMA_ENABLE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/dma_exit.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DMA_EXIT` writer"]
+pub type W = crate::W<DMA_EXIT_SPEC>;
+#[doc = "Field `DMA_EXIT` writer - Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation."]
+pub type DMA_EXIT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<DMA_EXIT_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation."]
+    #[inline(always)]
+    pub fn dma_exit(&mut self) -> DMA_EXIT_W<DMA_EXIT_SPEC> {
+        DMA_EXIT_W::new(self, 0)
+    }
+}
+#[doc = "AES-DMA exit config\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_exit::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DMA_EXIT_SPEC;
+impl crate::RegisterSpec for DMA_EXIT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`dma_exit::W`](W) writer structure"]
+impl crate::Writable for DMA_EXIT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_EXIT to value 0"]
+impl crate::Resettable for DMA_EXIT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/h_mem.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `H_MEM[%s]` reader"]
+pub type R = crate::R<H_MEM_SPEC>;
+#[doc = "Register `H_MEM[%s]` writer"]
+pub type W = crate::W<H_MEM_SPEC>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct H_MEM_SPEC;
+impl crate::RegisterSpec for H_MEM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`h_mem::R`](R) reader structure"]
+impl crate::Readable for H_MEM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`h_mem::W`](W) writer structure"]
+impl crate::Writable for H_MEM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets H_MEM[%s] to value 0"]
+impl crate::Resettable for H_MEM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/inc_sel.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `INC_SEL` reader"]
+pub type R = crate::R<INC_SEL_SPEC>;
+#[doc = "Register `INC_SEL` writer"]
+pub type W = crate::W<INC_SEL_SPEC>;
+#[doc = "Field `INC_SEL` reader - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
+pub type INC_SEL_R = crate::BitReader;
+#[doc = "Field `INC_SEL` writer - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
+pub type INC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
+    #[inline(always)]
+    pub fn inc_sel(&self) -> INC_SEL_R {
+        INC_SEL_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INC_SEL")
+            .field("inc_sel", &self.inc_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
+    #[inline(always)]
+    pub fn inc_sel(&mut self) -> INC_SEL_W<INC_SEL_SPEC> {
+        INC_SEL_W::new(self, 0)
+    }
+}
+#[doc = "Standard incrementing function configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`inc_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inc_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INC_SEL_SPEC;
+impl crate::RegisterSpec for INC_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`inc_sel::R`](R) reader structure"]
+impl crate::Readable for INC_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`inc_sel::W`](W) writer structure"]
+impl crate::Writable for INC_SEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INC_SEL to value 0"]
+impl crate::Resettable for INC_SEL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/int_clr.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` writer - Set this bit to 1 to clear AES interrupt."]
+pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to 1 to clear AES interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
+        INT_CLR_W::new(self, 0)
+    }
+}
+#[doc = "AES Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/int_ena.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `INT_ENA` reader - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
+pub type INT_ENA_R = crate::BitReader;
+#[doc = "Field `INT_ENA` writer - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
+pub type INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
+    #[inline(always)]
+    pub fn int_ena(&self) -> INT_ENA_R {
+        INT_ENA_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("int_ena", &self.int_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
+    #[inline(always)]
+    pub fn int_ena(&mut self) -> INT_ENA_W<INT_ENA_SPEC> {
+        INT_ENA_W::new(self, 0)
+    }
+}
+#[doc = "DMA-AES Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/iv_mem.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `IV_MEM[%s]` reader"]
+pub type R = crate::R<IV_MEM_SPEC>;
+#[doc = "Register `IV_MEM[%s]` writer"]
+pub type W = crate::W<IV_MEM_SPEC>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::Reg::read) this register and get [`iv_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IV_MEM_SPEC;
+impl crate::RegisterSpec for IV_MEM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`iv_mem::R`](R) reader structure"]
+impl crate::Readable for IV_MEM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`iv_mem::W`](W) writer structure"]
+impl crate::Writable for IV_MEM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IV_MEM[%s] to value 0"]
+impl crate::Resettable for IV_MEM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/j0_mem.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `J0_MEM[%s]` reader"]
+pub type R = crate::R<J0_MEM_SPEC>;
+#[doc = "Register `J0_MEM[%s]` writer"]
+pub type W = crate::W<J0_MEM_SPEC>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "The memory that stores J0\n\nYou can [`read`](crate::Reg::read) this register and get [`j0_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct J0_MEM_SPEC;
+impl crate::RegisterSpec for J0_MEM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`j0_mem::R`](R) reader structure"]
+impl crate::Readable for J0_MEM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`j0_mem::W`](W) writer structure"]
+impl crate::Writable for J0_MEM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets J0_MEM[%s] to value 0"]
+impl crate::Resettable for J0_MEM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/key.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `KEY[%s]` reader"]
+pub type R = crate::R<KEY_SPEC>;
+#[doc = "Register `KEY[%s]` writer"]
+pub type W = crate::W<KEY_SPEC>;
+#[doc = "Field `KEY` reader - Stores AES keys."]
+pub type KEY_R = crate::FieldReader<u32>;
+#[doc = "Field `KEY` writer - Stores AES keys."]
+pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
+impl R {
+    #[doc = "Bits 0:31 - Stores AES keys."]
+    #[inline(always)]
+    pub fn key(&self) -> KEY_R {
+        KEY_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("KEY").field("key", &self.key()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Stores AES keys."]
+    #[inline(always)]
+    pub fn key(&mut self) -> KEY_W<KEY_SPEC> {
+        KEY_W::new(self, 0)
+    }
+}
+#[doc = "AES key register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`key::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct KEY_SPEC;
+impl crate::RegisterSpec for KEY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`key::R`](R) reader structure"]
+impl crate::Readable for KEY_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`key::W`](W) writer structure"]
+impl crate::Writable for KEY_SPEC {
+    type Safety = crate::Safe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets KEY[%s] to value 0"]
+impl crate::Resettable for KEY_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/mode.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `MODE` reader"]
+pub type R = crate::R<MODE_SPEC>;
+#[doc = "Register `MODE` writer"]
+pub type W = crate::W<MODE_SPEC>;
+#[doc = "Field `MODE` reader - Defines the key length and the encryption/decryption of the AES accelerator."]
+pub type MODE_R = crate::FieldReader;
+#[doc = "Field `MODE` writer - Defines the key length and the encryption/decryption of the AES accelerator."]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:2 - Defines the key length and the encryption/decryption of the AES accelerator."]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Defines the key length and the encryption/decryption of the AES accelerator."]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
+        MODE_W::new(self, 0)
+    }
+}
+#[doc = "AES Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MODE_SPEC;
+impl crate::RegisterSpec for MODE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mode::R`](R) reader structure"]
+impl crate::Readable for MODE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
+impl crate::Writable for MODE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MODE to value 0"]
+impl crate::Resettable for MODE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/remainder_bit_num.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `REMAINDER_BIT_NUM` reader"]
+pub type R = crate::R<REMAINDER_BIT_NUM_SPEC>;
+#[doc = "Register `REMAINDER_BIT_NUM` writer"]
+pub type W = crate::W<REMAINDER_BIT_NUM_SPEC>;
+#[doc = "Field `REMAINDER_BIT_NUM` reader - Those bits stores the number of remainder bit."]
+pub type REMAINDER_BIT_NUM_R = crate::FieldReader;
+#[doc = "Field `REMAINDER_BIT_NUM` writer - Those bits stores the number of remainder bit."]
+pub type REMAINDER_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
+    #[inline(always)]
+    pub fn remainder_bit_num(&self) -> REMAINDER_BIT_NUM_R {
+        REMAINDER_BIT_NUM_R::new((self.bits & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("REMAINDER_BIT_NUM")
+            .field("remainder_bit_num", &self.remainder_bit_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
+    #[inline(always)]
+    pub fn remainder_bit_num(&mut self) -> REMAINDER_BIT_NUM_W<REMAINDER_BIT_NUM_SPEC> {
+        REMAINDER_BIT_NUM_W::new(self, 0)
+    }
+}
+#[doc = "AES remainder bit number register\n\nYou can [`read`](crate::Reg::read) this register and get [`remainder_bit_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remainder_bit_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct REMAINDER_BIT_NUM_SPEC;
+impl crate::RegisterSpec for REMAINDER_BIT_NUM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`remainder_bit_num::R`](R) reader structure"]
+impl crate::Readable for REMAINDER_BIT_NUM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`remainder_bit_num::W`](W) writer structure"]
+impl crate::Writable for REMAINDER_BIT_NUM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets REMAINDER_BIT_NUM to value 0"]
+impl crate::Resettable for REMAINDER_BIT_NUM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/state.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `STATE` reader"]
+pub type R = crate::R<STATE_SPEC>;
+#[doc = "Field `STATE` reader - Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done."]
+pub type STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:1 - Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done."]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new((self.bits & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATE")
+            .field("state", &self.state())
+            .finish()
+    }
+}
+#[doc = "AES state register\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATE_SPEC;
+impl crate::RegisterSpec for STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state::R`](R) reader structure"]
+impl crate::Readable for STATE_SPEC {}
+#[doc = "`reset()` method sets STATE to value 0"]
+impl crate::Resettable for STATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/t0_mem.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `T0_MEM[%s]` reader"]
+pub type R = crate::R<T0_MEM_SPEC>;
+#[doc = "Register `T0_MEM[%s]` writer"]
+pub type W = crate::W<T0_MEM_SPEC>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "The memory that stores T0\n\nYou can [`read`](crate::Reg::read) this register and get [`t0_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct T0_MEM_SPEC;
+impl crate::RegisterSpec for T0_MEM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`t0_mem::R`](R) reader structure"]
+impl crate::Readable for T0_MEM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`t0_mem::W`](W) writer structure"]
+impl crate::Writable for T0_MEM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets T0_MEM[%s] to value 0"]
+impl crate::Resettable for T0_MEM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/text_in.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `TEXT_IN[%s]` reader"]
+pub type R = crate::R<TEXT_IN_SPEC>;
+#[doc = "Register `TEXT_IN[%s]` writer"]
+pub type W = crate::W<TEXT_IN_SPEC>;
+#[doc = "Field `TEXT_IN` reader - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
+pub type TEXT_IN_R = crate::FieldReader<u32>;
+#[doc = "Field `TEXT_IN` writer - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
+pub type TEXT_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
+impl R {
+    #[doc = "Bits 0:31 - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
+    #[inline(always)]
+    pub fn text_in(&self) -> TEXT_IN_R {
+        TEXT_IN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TEXT_IN")
+            .field("text_in", &self.text_in())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
+    #[inline(always)]
+    pub fn text_in(&mut self) -> TEXT_IN_W<TEXT_IN_SPEC> {
+        TEXT_IN_W::new(self, 0)
+    }
+}
+#[doc = "Source data register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`text_in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TEXT_IN_SPEC;
+impl crate::RegisterSpec for TEXT_IN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`text_in::R`](R) reader structure"]
+impl crate::Readable for TEXT_IN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`text_in::W`](W) writer structure"]
+impl crate::Writable for TEXT_IN_SPEC {
+    type Safety = crate::Safe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TEXT_IN[%s] to value 0"]
+impl crate::Resettable for TEXT_IN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/text_out.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `TEXT_OUT[%s]` reader"]
+pub type R = crate::R<TEXT_OUT_SPEC>;
+#[doc = "Register `TEXT_OUT[%s]` writer"]
+pub type W = crate::W<TEXT_OUT_SPEC>;
+#[doc = "Field `TEXT_OUT` reader - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
+pub type TEXT_OUT_R = crate::FieldReader<u32>;
+#[doc = "Field `TEXT_OUT` writer - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
+pub type TEXT_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
+    #[inline(always)]
+    pub fn text_out(&self) -> TEXT_OUT_R {
+        TEXT_OUT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TEXT_OUT")
+            .field("text_out", &self.text_out())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
+    #[inline(always)]
+    pub fn text_out(&mut self) -> TEXT_OUT_W<TEXT_OUT_SPEC> {
+        TEXT_OUT_W::new(self, 0)
+    }
+}
+#[doc = "Result data register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`text_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TEXT_OUT_SPEC;
+impl crate::RegisterSpec for TEXT_OUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`text_out::R`](R) reader structure"]
+impl crate::Readable for TEXT_OUT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`text_out::W`](W) writer structure"]
+impl crate::Writable for TEXT_OUT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TEXT_OUT[%s] to value 0"]
+impl crate::Resettable for TEXT_OUT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/aes/trigger.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `TRIGGER` writer"]
+pub type W = crate::W<TRIGGER_SPEC>;
+#[doc = "Field `TRIGGER` writer - Set this bit to 1 to start AES calculation."]
+pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to 1 to start AES calculation."]
+    #[inline(always)]
+    pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
+        TRIGGER_W::new(self, 0)
+    }
+}
+#[doc = "AES trigger register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigger::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TRIGGER_SPEC;
+impl crate::RegisterSpec for TRIGGER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"]
+impl crate::Writable for TRIGGER_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TRIGGER to value 0"]
+impl crate::Resettable for TRIGGER_SPEC {
+    const RESET_VALUE: u32 = 0;
+}