feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/system/bt_lpck_div_frac.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `BT_LPCK_DIV_FRAC` reader"]
+pub type R = crate::R<BT_LPCK_DIV_FRAC_SPEC>;
+#[doc = "Register `BT_LPCK_DIV_FRAC` writer"]
+pub type W = crate::W<BT_LPCK_DIV_FRAC_SPEC>;
+#[doc = "Field `BT_LPCK_DIV_B` reader - This field is lower power clock frequent division factor b"]
+pub type BT_LPCK_DIV_B_R = crate::FieldReader<u16>;
+#[doc = "Field `BT_LPCK_DIV_B` writer - This field is lower power clock frequent division factor b"]
+pub type BT_LPCK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `BT_LPCK_DIV_A` reader - This field is lower power clock frequent division factor a"]
+pub type BT_LPCK_DIV_A_R = crate::FieldReader<u16>;
+#[doc = "Field `BT_LPCK_DIV_A` writer - This field is lower power clock frequent division factor a"]
+pub type BT_LPCK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `LPCLK_SEL_RTC_SLOW` reader - Set 1 to select rtc-slow clock as rtc low power clock"]
+pub type LPCLK_SEL_RTC_SLOW_R = crate::BitReader;
+#[doc = "Field `LPCLK_SEL_RTC_SLOW` writer - Set 1 to select rtc-slow clock as rtc low power clock"]
+pub type LPCLK_SEL_RTC_SLOW_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LPCLK_SEL_8M` reader - Set 1 to select 8m clock as rtc low power clock"]
+pub type LPCLK_SEL_8M_R = crate::BitReader;
+#[doc = "Field `LPCLK_SEL_8M` writer - Set 1 to select 8m clock as rtc low power clock"]
+pub type LPCLK_SEL_8M_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LPCLK_SEL_XTAL` reader - Set 1 to select xtal clock as rtc low power clock"]
+pub type LPCLK_SEL_XTAL_R = crate::BitReader;
+#[doc = "Field `LPCLK_SEL_XTAL` writer - Set 1 to select xtal clock as rtc low power clock"]
+pub type LPCLK_SEL_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LPCLK_SEL_XTAL32K` reader - Set 1 to select xtal32k clock as low power clock"]
+pub type LPCLK_SEL_XTAL32K_R = crate::BitReader;
+#[doc = "Field `LPCLK_SEL_XTAL32K` writer - Set 1 to select xtal32k clock as low power clock"]
+pub type LPCLK_SEL_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LPCLK_RTC_EN` reader - Set 1 to enable RTC low power clock"]
+pub type LPCLK_RTC_EN_R = crate::BitReader;
+#[doc = "Field `LPCLK_RTC_EN` writer - Set 1 to enable RTC low power clock"]
+pub type LPCLK_RTC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
+    #[inline(always)]
+    pub fn bt_lpck_div_b(&self) -> BT_LPCK_DIV_B_R {
+        BT_LPCK_DIV_B_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 12:23 - This field is lower power clock frequent division factor a"]
+    #[inline(always)]
+    pub fn bt_lpck_div_a(&self) -> BT_LPCK_DIV_A_R {
+        BT_LPCK_DIV_A_R::new(((self.bits >> 12) & 0x0fff) as u16)
+    }
+    #[doc = "Bit 24 - Set 1 to select rtc-slow clock as rtc low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_rtc_slow(&self) -> LPCLK_SEL_RTC_SLOW_R {
+        LPCLK_SEL_RTC_SLOW_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - Set 1 to select 8m clock as rtc low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_8m(&self) -> LPCLK_SEL_8M_R {
+        LPCLK_SEL_8M_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - Set 1 to select xtal clock as rtc low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_xtal(&self) -> LPCLK_SEL_XTAL_R {
+        LPCLK_SEL_XTAL_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - Set 1 to select xtal32k clock as low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_xtal32k(&self) -> LPCLK_SEL_XTAL32K_R {
+        LPCLK_SEL_XTAL32K_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - Set 1 to enable RTC low power clock"]
+    #[inline(always)]
+    pub fn lpclk_rtc_en(&self) -> LPCLK_RTC_EN_R {
+        LPCLK_RTC_EN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BT_LPCK_DIV_FRAC")
+            .field("bt_lpck_div_b", &self.bt_lpck_div_b())
+            .field("bt_lpck_div_a", &self.bt_lpck_div_a())
+            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
+            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
+            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
+            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
+            .field("lpclk_rtc_en", &self.lpclk_rtc_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
+    #[inline(always)]
+    pub fn bt_lpck_div_b(&mut self) -> BT_LPCK_DIV_B_W<BT_LPCK_DIV_FRAC_SPEC> {
+        BT_LPCK_DIV_B_W::new(self, 0)
+    }
+    #[doc = "Bits 12:23 - This field is lower power clock frequent division factor a"]
+    #[inline(always)]
+    pub fn bt_lpck_div_a(&mut self) -> BT_LPCK_DIV_A_W<BT_LPCK_DIV_FRAC_SPEC> {
+        BT_LPCK_DIV_A_W::new(self, 12)
+    }
+    #[doc = "Bit 24 - Set 1 to select rtc-slow clock as rtc low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_rtc_slow(&mut self) -> LPCLK_SEL_RTC_SLOW_W<BT_LPCK_DIV_FRAC_SPEC> {
+        LPCLK_SEL_RTC_SLOW_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - Set 1 to select 8m clock as rtc low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_8m(&mut self) -> LPCLK_SEL_8M_W<BT_LPCK_DIV_FRAC_SPEC> {
+        LPCLK_SEL_8M_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - Set 1 to select xtal clock as rtc low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_xtal(&mut self) -> LPCLK_SEL_XTAL_W<BT_LPCK_DIV_FRAC_SPEC> {
+        LPCLK_SEL_XTAL_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - Set 1 to select xtal32k clock as low power clock"]
+    #[inline(always)]
+    pub fn lpclk_sel_xtal32k(&mut self) -> LPCLK_SEL_XTAL32K_W<BT_LPCK_DIV_FRAC_SPEC> {
+        LPCLK_SEL_XTAL32K_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - Set 1 to enable RTC low power clock"]
+    #[inline(always)]
+    pub fn lpclk_rtc_en(&mut self) -> LPCLK_RTC_EN_W<BT_LPCK_DIV_FRAC_SPEC> {
+        LPCLK_RTC_EN_W::new(self, 28)
+    }
+}
+#[doc = "low power clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bt_lpck_div_frac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bt_lpck_div_frac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BT_LPCK_DIV_FRAC_SPEC;
+impl crate::RegisterSpec for BT_LPCK_DIV_FRAC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bt_lpck_div_frac::R`](R) reader structure"]
+impl crate::Readable for BT_LPCK_DIV_FRAC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`bt_lpck_div_frac::W`](W) writer structure"]
+impl crate::Writable for BT_LPCK_DIV_FRAC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BT_LPCK_DIV_FRAC to value 0x0200_1001"]
+impl crate::Resettable for BT_LPCK_DIV_FRAC_SPEC {
+    const RESET_VALUE: u32 = 0x0200_1001;
+}

vendor/esp32s3/src/system/bt_lpck_div_int.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `BT_LPCK_DIV_INT` reader"]
+pub type R = crate::R<BT_LPCK_DIV_INT_SPEC>;
+#[doc = "Register `BT_LPCK_DIV_INT` writer"]
+pub type W = crate::W<BT_LPCK_DIV_INT_SPEC>;
+#[doc = "Field `BT_LPCK_DIV_NUM` reader - This field is lower power clock frequent division factor"]
+pub type BT_LPCK_DIV_NUM_R = crate::FieldReader<u16>;
+#[doc = "Field `BT_LPCK_DIV_NUM` writer - This field is lower power clock frequent division factor"]
+pub type BT_LPCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+impl R {
+    #[doc = "Bits 0:11 - This field is lower power clock frequent division factor"]
+    #[inline(always)]
+    pub fn bt_lpck_div_num(&self) -> BT_LPCK_DIV_NUM_R {
+        BT_LPCK_DIV_NUM_R::new((self.bits & 0x0fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BT_LPCK_DIV_INT")
+            .field("bt_lpck_div_num", &self.bt_lpck_div_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - This field is lower power clock frequent division factor"]
+    #[inline(always)]
+    pub fn bt_lpck_div_num(&mut self) -> BT_LPCK_DIV_NUM_W<BT_LPCK_DIV_INT_SPEC> {
+        BT_LPCK_DIV_NUM_W::new(self, 0)
+    }
+}
+#[doc = "low power clock frequent division factor configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`bt_lpck_div_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bt_lpck_div_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BT_LPCK_DIV_INT_SPEC;
+impl crate::RegisterSpec for BT_LPCK_DIV_INT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bt_lpck_div_int::R`](R) reader structure"]
+impl crate::Readable for BT_LPCK_DIV_INT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`bt_lpck_div_int::W`](W) writer structure"]
+impl crate::Writable for BT_LPCK_DIV_INT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BT_LPCK_DIV_INT to value 0xff"]
+impl crate::Resettable for BT_LPCK_DIV_INT_SPEC {
+    const RESET_VALUE: u32 = 0xff;
+}

vendor/esp32s3/src/system/cache_control.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `CACHE_CONTROL` reader"]
+pub type R = crate::R<CACHE_CONTROL_SPEC>;
+#[doc = "Register `CACHE_CONTROL` writer"]
+pub type W = crate::W<CACHE_CONTROL_SPEC>;
+#[doc = "Field `ICACHE_CLK_ON` reader - Set 1 to enable icache clock"]
+pub type ICACHE_CLK_ON_R = crate::BitReader;
+#[doc = "Field `ICACHE_CLK_ON` writer - Set 1 to enable icache clock"]
+pub type ICACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_RESET` reader - Set 1 to let icache reset"]
+pub type ICACHE_RESET_R = crate::BitReader;
+#[doc = "Field `ICACHE_RESET` writer - Set 1 to let icache reset"]
+pub type ICACHE_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_CLK_ON` reader - Set 1 to enable dcache clock"]
+pub type DCACHE_CLK_ON_R = crate::BitReader;
+#[doc = "Field `DCACHE_CLK_ON` writer - Set 1 to enable dcache clock"]
+pub type DCACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_RESET` reader - Set 1 to let dcache reset"]
+pub type DCACHE_RESET_R = crate::BitReader;
+#[doc = "Field `DCACHE_RESET` writer - Set 1 to let dcache reset"]
+pub type DCACHE_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to enable icache clock"]
+    #[inline(always)]
+    pub fn icache_clk_on(&self) -> ICACHE_CLK_ON_R {
+        ICACHE_CLK_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let icache reset"]
+    #[inline(always)]
+    pub fn icache_reset(&self) -> ICACHE_RESET_R {
+        ICACHE_RESET_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to enable dcache clock"]
+    #[inline(always)]
+    pub fn dcache_clk_on(&self) -> DCACHE_CLK_ON_R {
+        DCACHE_CLK_ON_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to let dcache reset"]
+    #[inline(always)]
+    pub fn dcache_reset(&self) -> DCACHE_RESET_R {
+        DCACHE_RESET_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_CONTROL")
+            .field("icache_clk_on", &self.icache_clk_on())
+            .field("icache_reset", &self.icache_reset())
+            .field("dcache_clk_on", &self.dcache_clk_on())
+            .field("dcache_reset", &self.dcache_reset())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to enable icache clock"]
+    #[inline(always)]
+    pub fn icache_clk_on(&mut self) -> ICACHE_CLK_ON_W<CACHE_CONTROL_SPEC> {
+        ICACHE_CLK_ON_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let icache reset"]
+    #[inline(always)]
+    pub fn icache_reset(&mut self) -> ICACHE_RESET_W<CACHE_CONTROL_SPEC> {
+        ICACHE_RESET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to enable dcache clock"]
+    #[inline(always)]
+    pub fn dcache_clk_on(&mut self) -> DCACHE_CLK_ON_W<CACHE_CONTROL_SPEC> {
+        DCACHE_CLK_ON_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to let dcache reset"]
+    #[inline(always)]
+    pub fn dcache_reset(&mut self) -> DCACHE_RESET_W<CACHE_CONTROL_SPEC> {
+        DCACHE_RESET_W::new(self, 3)
+    }
+}
+#[doc = "Cache control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_CONTROL_SPEC;
+impl crate::RegisterSpec for CACHE_CONTROL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_control::R`](R) reader structure"]
+impl crate::Readable for CACHE_CONTROL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_control::W`](W) writer structure"]
+impl crate::Writable for CACHE_CONTROL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_CONTROL to value 0x05"]
+impl crate::Resettable for CACHE_CONTROL_SPEC {
+    const RESET_VALUE: u32 = 0x05;
+}

vendor/esp32s3/src/system/clock_gate.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CLOCK_GATE` reader"]
+pub type R = crate::R<CLOCK_GATE_SPEC>;
+#[doc = "Register `CLOCK_GATE` writer"]
+pub type W = crate::W<CLOCK_GATE_SPEC>;
+#[doc = "Field `CLK_EN` reader - ******* Description ***********"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - ******* Description ***********"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLOCK_GATE")
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
+        CLK_EN_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLOCK_GATE_SPEC;
+impl crate::RegisterSpec for CLOCK_GATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
+impl crate::Readable for CLOCK_GATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
+impl crate::Writable for CLOCK_GATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"]
+impl crate::Resettable for CLOCK_GATE_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/system/comb_pvt_err_hvt_site0.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_HVT_SITE0` reader"]
+pub type R = crate::R<COMB_PVT_ERR_HVT_SITE0_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_HVT_SITE0` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_HVT_SITE0_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_hvt_site0(&self) -> COMB_TIMING_ERR_CNT_HVT_SITE0_R {
+        COMB_TIMING_ERR_CNT_HVT_SITE0_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_HVT_SITE0")
+            .field(
+                "comb_timing_err_cnt_hvt_site0",
+                &self.comb_timing_err_cnt_hvt_site0(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_hvt_site0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_HVT_SITE0_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_hvt_site0::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_HVT_SITE0_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_HVT_SITE0 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_HVT_SITE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_hvt_site1.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_HVT_SITE1` reader"]
+pub type R = crate::R<COMB_PVT_ERR_HVT_SITE1_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_HVT_SITE1` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_HVT_SITE1_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_hvt_site1(&self) -> COMB_TIMING_ERR_CNT_HVT_SITE1_R {
+        COMB_TIMING_ERR_CNT_HVT_SITE1_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_HVT_SITE1")
+            .field(
+                "comb_timing_err_cnt_hvt_site1",
+                &self.comb_timing_err_cnt_hvt_site1(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_hvt_site1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_HVT_SITE1_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_hvt_site1::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_HVT_SITE1_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_HVT_SITE1 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_HVT_SITE1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_hvt_site2.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_HVT_SITE2` reader"]
+pub type R = crate::R<COMB_PVT_ERR_HVT_SITE2_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_HVT_SITE2` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_HVT_SITE2_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_hvt_site2(&self) -> COMB_TIMING_ERR_CNT_HVT_SITE2_R {
+        COMB_TIMING_ERR_CNT_HVT_SITE2_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_HVT_SITE2")
+            .field(
+                "comb_timing_err_cnt_hvt_site2",
+                &self.comb_timing_err_cnt_hvt_site2(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_hvt_site2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_HVT_SITE2_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_hvt_site2::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_HVT_SITE2_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_HVT_SITE2 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_HVT_SITE2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_hvt_site3.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_HVT_SITE3` reader"]
+pub type R = crate::R<COMB_PVT_ERR_HVT_SITE3_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_HVT_SITE3` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_HVT_SITE3_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_hvt_site3(&self) -> COMB_TIMING_ERR_CNT_HVT_SITE3_R {
+        COMB_TIMING_ERR_CNT_HVT_SITE3_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_HVT_SITE3")
+            .field(
+                "comb_timing_err_cnt_hvt_site3",
+                &self.comb_timing_err_cnt_hvt_site3(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_hvt_site3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_HVT_SITE3_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_hvt_site3::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_HVT_SITE3_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_HVT_SITE3 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_HVT_SITE3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_lvt_site0.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_LVT_SITE0` reader"]
+pub type R = crate::R<COMB_PVT_ERR_LVT_SITE0_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_LVT_SITE0` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_LVT_SITE0_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_lvt_site0(&self) -> COMB_TIMING_ERR_CNT_LVT_SITE0_R {
+        COMB_TIMING_ERR_CNT_LVT_SITE0_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_LVT_SITE0")
+            .field(
+                "comb_timing_err_cnt_lvt_site0",
+                &self.comb_timing_err_cnt_lvt_site0(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_lvt_site0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_LVT_SITE0_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_lvt_site0::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_LVT_SITE0_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_LVT_SITE0 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_LVT_SITE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_lvt_site1.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_LVT_SITE1` reader"]
+pub type R = crate::R<COMB_PVT_ERR_LVT_SITE1_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_LVT_SITE1` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_LVT_SITE1_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_lvt_site1(&self) -> COMB_TIMING_ERR_CNT_LVT_SITE1_R {
+        COMB_TIMING_ERR_CNT_LVT_SITE1_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_LVT_SITE1")
+            .field(
+                "comb_timing_err_cnt_lvt_site1",
+                &self.comb_timing_err_cnt_lvt_site1(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_lvt_site1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_LVT_SITE1_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_lvt_site1::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_LVT_SITE1_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_LVT_SITE1 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_LVT_SITE1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_lvt_site2.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_LVT_SITE2` reader"]
+pub type R = crate::R<COMB_PVT_ERR_LVT_SITE2_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_LVT_SITE2` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_LVT_SITE2_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_lvt_site2(&self) -> COMB_TIMING_ERR_CNT_LVT_SITE2_R {
+        COMB_TIMING_ERR_CNT_LVT_SITE2_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_LVT_SITE2")
+            .field(
+                "comb_timing_err_cnt_lvt_site2",
+                &self.comb_timing_err_cnt_lvt_site2(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_lvt_site2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_LVT_SITE2_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_lvt_site2::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_LVT_SITE2_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_LVT_SITE2 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_LVT_SITE2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_lvt_site3.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_LVT_SITE3` reader"]
+pub type R = crate::R<COMB_PVT_ERR_LVT_SITE3_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_LVT_SITE3` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_LVT_SITE3_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_lvt_site3(&self) -> COMB_TIMING_ERR_CNT_LVT_SITE3_R {
+        COMB_TIMING_ERR_CNT_LVT_SITE3_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_LVT_SITE3")
+            .field(
+                "comb_timing_err_cnt_lvt_site3",
+                &self.comb_timing_err_cnt_lvt_site3(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_lvt_site3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_LVT_SITE3_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_lvt_site3::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_LVT_SITE3_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_LVT_SITE3 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_LVT_SITE3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_nvt_site0.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_NVT_SITE0` reader"]
+pub type R = crate::R<COMB_PVT_ERR_NVT_SITE0_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_NVT_SITE0` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_NVT_SITE0_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_nvt_site0(&self) -> COMB_TIMING_ERR_CNT_NVT_SITE0_R {
+        COMB_TIMING_ERR_CNT_NVT_SITE0_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_NVT_SITE0")
+            .field(
+                "comb_timing_err_cnt_nvt_site0",
+                &self.comb_timing_err_cnt_nvt_site0(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_nvt_site0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_NVT_SITE0_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_nvt_site0::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_NVT_SITE0_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_NVT_SITE0 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_NVT_SITE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_nvt_site1.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_NVT_SITE1` reader"]
+pub type R = crate::R<COMB_PVT_ERR_NVT_SITE1_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_NVT_SITE1` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_NVT_SITE1_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_nvt_site1(&self) -> COMB_TIMING_ERR_CNT_NVT_SITE1_R {
+        COMB_TIMING_ERR_CNT_NVT_SITE1_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_NVT_SITE1")
+            .field(
+                "comb_timing_err_cnt_nvt_site1",
+                &self.comb_timing_err_cnt_nvt_site1(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_nvt_site1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_NVT_SITE1_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_nvt_site1::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_NVT_SITE1_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_NVT_SITE1 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_NVT_SITE1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_nvt_site2.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_NVT_SITE2` reader"]
+pub type R = crate::R<COMB_PVT_ERR_NVT_SITE2_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_NVT_SITE2` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_NVT_SITE2_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_nvt_site2(&self) -> COMB_TIMING_ERR_CNT_NVT_SITE2_R {
+        COMB_TIMING_ERR_CNT_NVT_SITE2_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_NVT_SITE2")
+            .field(
+                "comb_timing_err_cnt_nvt_site2",
+                &self.comb_timing_err_cnt_nvt_site2(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_nvt_site2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_NVT_SITE2_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_nvt_site2::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_NVT_SITE2_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_NVT_SITE2 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_NVT_SITE2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_err_nvt_site3.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `COMB_PVT_ERR_NVT_SITE3` reader"]
+pub type R = crate::R<COMB_PVT_ERR_NVT_SITE3_SPEC>;
+#[doc = "Field `COMB_TIMING_ERR_CNT_NVT_SITE3` reader - ******* Description ***********"]
+pub type COMB_TIMING_ERR_CNT_NVT_SITE3_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_timing_err_cnt_nvt_site3(&self) -> COMB_TIMING_ERR_CNT_NVT_SITE3_R {
+        COMB_TIMING_ERR_CNT_NVT_SITE3_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_ERR_NVT_SITE3")
+            .field(
+                "comb_timing_err_cnt_nvt_site3",
+                &self.comb_timing_err_cnt_nvt_site3(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_err_nvt_site3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_ERR_NVT_SITE3_SPEC;
+impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_err_nvt_site3::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_ERR_NVT_SITE3_SPEC {}
+#[doc = "`reset()` method sets COMB_PVT_ERR_NVT_SITE3 to value 0"]
+impl crate::Resettable for COMB_PVT_ERR_NVT_SITE3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/comb_pvt_hvt_conf.rs

@@ -0,0 +1,69 @@
+#[doc = "Register `COMB_PVT_HVT_CONF` reader"]
+pub type R = crate::R<COMB_PVT_HVT_CONF_SPEC>;
+#[doc = "Register `COMB_PVT_HVT_CONF` writer"]
+pub type W = crate::W<COMB_PVT_HVT_CONF_SPEC>;
+#[doc = "Field `COMB_PATH_LEN_HVT` reader - ******* Description ***********"]
+pub type COMB_PATH_LEN_HVT_R = crate::FieldReader;
+#[doc = "Field `COMB_PATH_LEN_HVT` writer - ******* Description ***********"]
+pub type COMB_PATH_LEN_HVT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `COMB_ERR_CNT_CLR_HVT` writer - ******* Description ***********"]
+pub type COMB_ERR_CNT_CLR_HVT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COMB_PVT_MONITOR_EN_HVT` reader - ******* Description ***********"]
+pub type COMB_PVT_MONITOR_EN_HVT_R = crate::BitReader;
+#[doc = "Field `COMB_PVT_MONITOR_EN_HVT` writer - ******* Description ***********"]
+pub type COMB_PVT_MONITOR_EN_HVT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_path_len_hvt(&self) -> COMB_PATH_LEN_HVT_R {
+        COMB_PATH_LEN_HVT_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 6 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_pvt_monitor_en_hvt(&self) -> COMB_PVT_MONITOR_EN_HVT_R {
+        COMB_PVT_MONITOR_EN_HVT_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_HVT_CONF")
+            .field("comb_path_len_hvt", &self.comb_path_len_hvt())
+            .field("comb_pvt_monitor_en_hvt", &self.comb_pvt_monitor_en_hvt())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_path_len_hvt(&mut self) -> COMB_PATH_LEN_HVT_W<COMB_PVT_HVT_CONF_SPEC> {
+        COMB_PATH_LEN_HVT_W::new(self, 0)
+    }
+    #[doc = "Bit 5 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_err_cnt_clr_hvt(&mut self) -> COMB_ERR_CNT_CLR_HVT_W<COMB_PVT_HVT_CONF_SPEC> {
+        COMB_ERR_CNT_CLR_HVT_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_pvt_monitor_en_hvt(&mut self) -> COMB_PVT_MONITOR_EN_HVT_W<COMB_PVT_HVT_CONF_SPEC> {
+        COMB_PVT_MONITOR_EN_HVT_W::new(self, 6)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_hvt_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comb_pvt_hvt_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_HVT_CONF_SPEC;
+impl crate::RegisterSpec for COMB_PVT_HVT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_hvt_conf::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_HVT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`comb_pvt_hvt_conf::W`](W) writer structure"]
+impl crate::Writable for COMB_PVT_HVT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets COMB_PVT_HVT_CONF to value 0x03"]
+impl crate::Resettable for COMB_PVT_HVT_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x03;
+}

vendor/esp32s3/src/system/comb_pvt_lvt_conf.rs

@@ -0,0 +1,69 @@
+#[doc = "Register `COMB_PVT_LVT_CONF` reader"]
+pub type R = crate::R<COMB_PVT_LVT_CONF_SPEC>;
+#[doc = "Register `COMB_PVT_LVT_CONF` writer"]
+pub type W = crate::W<COMB_PVT_LVT_CONF_SPEC>;
+#[doc = "Field `COMB_PATH_LEN_LVT` reader - ******* Description ***********"]
+pub type COMB_PATH_LEN_LVT_R = crate::FieldReader;
+#[doc = "Field `COMB_PATH_LEN_LVT` writer - ******* Description ***********"]
+pub type COMB_PATH_LEN_LVT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `COMB_ERR_CNT_CLR_LVT` writer - ******* Description ***********"]
+pub type COMB_ERR_CNT_CLR_LVT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COMB_PVT_MONITOR_EN_LVT` reader - ******* Description ***********"]
+pub type COMB_PVT_MONITOR_EN_LVT_R = crate::BitReader;
+#[doc = "Field `COMB_PVT_MONITOR_EN_LVT` writer - ******* Description ***********"]
+pub type COMB_PVT_MONITOR_EN_LVT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_path_len_lvt(&self) -> COMB_PATH_LEN_LVT_R {
+        COMB_PATH_LEN_LVT_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 6 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_pvt_monitor_en_lvt(&self) -> COMB_PVT_MONITOR_EN_LVT_R {
+        COMB_PVT_MONITOR_EN_LVT_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_LVT_CONF")
+            .field("comb_path_len_lvt", &self.comb_path_len_lvt())
+            .field("comb_pvt_monitor_en_lvt", &self.comb_pvt_monitor_en_lvt())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_path_len_lvt(&mut self) -> COMB_PATH_LEN_LVT_W<COMB_PVT_LVT_CONF_SPEC> {
+        COMB_PATH_LEN_LVT_W::new(self, 0)
+    }
+    #[doc = "Bit 5 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_err_cnt_clr_lvt(&mut self) -> COMB_ERR_CNT_CLR_LVT_W<COMB_PVT_LVT_CONF_SPEC> {
+        COMB_ERR_CNT_CLR_LVT_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_pvt_monitor_en_lvt(&mut self) -> COMB_PVT_MONITOR_EN_LVT_W<COMB_PVT_LVT_CONF_SPEC> {
+        COMB_PVT_MONITOR_EN_LVT_W::new(self, 6)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_lvt_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comb_pvt_lvt_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_LVT_CONF_SPEC;
+impl crate::RegisterSpec for COMB_PVT_LVT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_lvt_conf::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_LVT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`comb_pvt_lvt_conf::W`](W) writer structure"]
+impl crate::Writable for COMB_PVT_LVT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets COMB_PVT_LVT_CONF to value 0x03"]
+impl crate::Resettable for COMB_PVT_LVT_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x03;
+}

vendor/esp32s3/src/system/comb_pvt_nvt_conf.rs

@@ -0,0 +1,69 @@
+#[doc = "Register `COMB_PVT_NVT_CONF` reader"]
+pub type R = crate::R<COMB_PVT_NVT_CONF_SPEC>;
+#[doc = "Register `COMB_PVT_NVT_CONF` writer"]
+pub type W = crate::W<COMB_PVT_NVT_CONF_SPEC>;
+#[doc = "Field `COMB_PATH_LEN_NVT` reader - ******* Description ***********"]
+pub type COMB_PATH_LEN_NVT_R = crate::FieldReader;
+#[doc = "Field `COMB_PATH_LEN_NVT` writer - ******* Description ***********"]
+pub type COMB_PATH_LEN_NVT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `COMB_ERR_CNT_CLR_NVT` writer - ******* Description ***********"]
+pub type COMB_ERR_CNT_CLR_NVT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COMB_PVT_MONITOR_EN_NVT` reader - ******* Description ***********"]
+pub type COMB_PVT_MONITOR_EN_NVT_R = crate::BitReader;
+#[doc = "Field `COMB_PVT_MONITOR_EN_NVT` writer - ******* Description ***********"]
+pub type COMB_PVT_MONITOR_EN_NVT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_path_len_nvt(&self) -> COMB_PATH_LEN_NVT_R {
+        COMB_PATH_LEN_NVT_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 6 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_pvt_monitor_en_nvt(&self) -> COMB_PVT_MONITOR_EN_NVT_R {
+        COMB_PVT_MONITOR_EN_NVT_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COMB_PVT_NVT_CONF")
+            .field("comb_path_len_nvt", &self.comb_path_len_nvt())
+            .field("comb_pvt_monitor_en_nvt", &self.comb_pvt_monitor_en_nvt())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_path_len_nvt(&mut self) -> COMB_PATH_LEN_NVT_W<COMB_PVT_NVT_CONF_SPEC> {
+        COMB_PATH_LEN_NVT_W::new(self, 0)
+    }
+    #[doc = "Bit 5 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_err_cnt_clr_nvt(&mut self) -> COMB_ERR_CNT_CLR_NVT_W<COMB_PVT_NVT_CONF_SPEC> {
+        COMB_ERR_CNT_CLR_NVT_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn comb_pvt_monitor_en_nvt(&mut self) -> COMB_PVT_MONITOR_EN_NVT_W<COMB_PVT_NVT_CONF_SPEC> {
+        COMB_PVT_MONITOR_EN_NVT_W::new(self, 6)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`comb_pvt_nvt_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comb_pvt_nvt_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMB_PVT_NVT_CONF_SPEC;
+impl crate::RegisterSpec for COMB_PVT_NVT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`comb_pvt_nvt_conf::R`](R) reader structure"]
+impl crate::Readable for COMB_PVT_NVT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`comb_pvt_nvt_conf::W`](W) writer structure"]
+impl crate::Writable for COMB_PVT_NVT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets COMB_PVT_NVT_CONF to value 0x03"]
+impl crate::Resettable for COMB_PVT_NVT_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x03;
+}

vendor/esp32s3/src/system/core_1_control_0.rs

@@ -0,0 +1,82 @@
+#[doc = "Register `CORE_1_CONTROL_0` reader"]
+pub type R = crate::R<CORE_1_CONTROL_0_SPEC>;
+#[doc = "Register `CORE_1_CONTROL_0` writer"]
+pub type W = crate::W<CORE_1_CONTROL_0_SPEC>;
+#[doc = "Field `CONTROL_CORE_1_RUNSTALL` reader - Set 1 to stall core1"]
+pub type CONTROL_CORE_1_RUNSTALL_R = crate::BitReader;
+#[doc = "Field `CONTROL_CORE_1_RUNSTALL` writer - Set 1 to stall core1"]
+pub type CONTROL_CORE_1_RUNSTALL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CONTROL_CORE_1_CLKGATE_EN` reader - Set 1 to open core1 clock"]
+pub type CONTROL_CORE_1_CLKGATE_EN_R = crate::BitReader;
+#[doc = "Field `CONTROL_CORE_1_CLKGATE_EN` writer - Set 1 to open core1 clock"]
+pub type CONTROL_CORE_1_CLKGATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CONTROL_CORE_1_RESETING` reader - Set 1 to let core1 reset"]
+pub type CONTROL_CORE_1_RESETING_R = crate::BitReader;
+#[doc = "Field `CONTROL_CORE_1_RESETING` writer - Set 1 to let core1 reset"]
+pub type CONTROL_CORE_1_RESETING_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to stall core1"]
+    #[inline(always)]
+    pub fn control_core_1_runstall(&self) -> CONTROL_CORE_1_RUNSTALL_R {
+        CONTROL_CORE_1_RUNSTALL_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to open core1 clock"]
+    #[inline(always)]
+    pub fn control_core_1_clkgate_en(&self) -> CONTROL_CORE_1_CLKGATE_EN_R {
+        CONTROL_CORE_1_CLKGATE_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to let core1 reset"]
+    #[inline(always)]
+    pub fn control_core_1_reseting(&self) -> CONTROL_CORE_1_RESETING_R {
+        CONTROL_CORE_1_RESETING_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_CONTROL_0")
+            .field("control_core_1_runstall", &self.control_core_1_runstall())
+            .field(
+                "control_core_1_clkgate_en",
+                &self.control_core_1_clkgate_en(),
+            )
+            .field("control_core_1_reseting", &self.control_core_1_reseting())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to stall core1"]
+    #[inline(always)]
+    pub fn control_core_1_runstall(&mut self) -> CONTROL_CORE_1_RUNSTALL_W<CORE_1_CONTROL_0_SPEC> {
+        CONTROL_CORE_1_RUNSTALL_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to open core1 clock"]
+    #[inline(always)]
+    pub fn control_core_1_clkgate_en(
+        &mut self,
+    ) -> CONTROL_CORE_1_CLKGATE_EN_W<CORE_1_CONTROL_0_SPEC> {
+        CONTROL_CORE_1_CLKGATE_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to let core1 reset"]
+    #[inline(always)]
+    pub fn control_core_1_reseting(&mut self) -> CONTROL_CORE_1_RESETING_W<CORE_1_CONTROL_0_SPEC> {
+        CONTROL_CORE_1_RESETING_W::new(self, 2)
+    }
+}
+#[doc = "Core0 control regiter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_control_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_control_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_CONTROL_0_SPEC;
+impl crate::RegisterSpec for CORE_1_CONTROL_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_control_0::R`](R) reader structure"]
+impl crate::Readable for CORE_1_CONTROL_0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_control_0::W`](W) writer structure"]
+impl crate::Writable for CORE_1_CONTROL_0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_CONTROL_0 to value 0x04"]
+impl crate::Resettable for CORE_1_CONTROL_0_SPEC {
+    const RESET_VALUE: u32 = 0x04;
+}

vendor/esp32s3/src/system/core_1_control_1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_CONTROL_1` reader"]
+pub type R = crate::R<CORE_1_CONTROL_1_SPEC>;
+#[doc = "Register `CORE_1_CONTROL_1` writer"]
+pub type W = crate::W<CORE_1_CONTROL_1_SPEC>;
+#[doc = "Field `CONTROL_CORE_1_MESSAGE` reader - it's only a R/W register, no function, software can write any value"]
+pub type CONTROL_CORE_1_MESSAGE_R = crate::FieldReader<u32>;
+#[doc = "Field `CONTROL_CORE_1_MESSAGE` writer - it's only a R/W register, no function, software can write any value"]
+pub type CONTROL_CORE_1_MESSAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - it's only a R/W register, no function, software can write any value"]
+    #[inline(always)]
+    pub fn control_core_1_message(&self) -> CONTROL_CORE_1_MESSAGE_R {
+        CONTROL_CORE_1_MESSAGE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_CONTROL_1")
+            .field("control_core_1_message", &self.control_core_1_message())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - it's only a R/W register, no function, software can write any value"]
+    #[inline(always)]
+    pub fn control_core_1_message(&mut self) -> CONTROL_CORE_1_MESSAGE_W<CORE_1_CONTROL_1_SPEC> {
+        CONTROL_CORE_1_MESSAGE_W::new(self, 0)
+    }
+}
+#[doc = "Core0 control regiter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_control_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_control_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_CONTROL_1_SPEC;
+impl crate::RegisterSpec for CORE_1_CONTROL_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_control_1::R`](R) reader structure"]
+impl crate::Readable for CORE_1_CONTROL_1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_control_1::W`](W) writer structure"]
+impl crate::Writable for CORE_1_CONTROL_1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_CONTROL_1 to value 0"]
+impl crate::Resettable for CORE_1_CONTROL_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/cpu_intr_from_cpu_0.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CPU_INTR_FROM_CPU_0` reader"]
+pub type R = crate::R<CPU_INTR_FROM_CPU_0_SPEC>;
+#[doc = "Register `CPU_INTR_FROM_CPU_0` writer"]
+pub type W = crate::W<CPU_INTR_FROM_CPU_0_SPEC>;
+#[doc = "Field `CPU_INTR_FROM_CPU_0` reader - Set 1 to generate cpu interrupt 0"]
+pub type CPU_INTR_FROM_CPU_0_R = crate::BitReader;
+#[doc = "Field `CPU_INTR_FROM_CPU_0` writer - Set 1 to generate cpu interrupt 0"]
+pub type CPU_INTR_FROM_CPU_0_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 0"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_0(&self) -> CPU_INTR_FROM_CPU_0_R {
+        CPU_INTR_FROM_CPU_0_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_INTR_FROM_CPU_0")
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 0"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_0(&mut self) -> CPU_INTR_FROM_CPU_0_W<CPU_INTR_FROM_CPU_0_SPEC> {
+        CPU_INTR_FROM_CPU_0_W::new(self, 0)
+    }
+}
+#[doc = "interrupt source register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_INTR_FROM_CPU_0_SPEC;
+impl crate::RegisterSpec for CPU_INTR_FROM_CPU_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_intr_from_cpu_0::R`](R) reader structure"]
+impl crate::Readable for CPU_INTR_FROM_CPU_0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_intr_from_cpu_0::W`](W) writer structure"]
+impl crate::Writable for CPU_INTR_FROM_CPU_0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_INTR_FROM_CPU_0 to value 0"]
+impl crate::Resettable for CPU_INTR_FROM_CPU_0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/cpu_intr_from_cpu_1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CPU_INTR_FROM_CPU_1` reader"]
+pub type R = crate::R<CPU_INTR_FROM_CPU_1_SPEC>;
+#[doc = "Register `CPU_INTR_FROM_CPU_1` writer"]
+pub type W = crate::W<CPU_INTR_FROM_CPU_1_SPEC>;
+#[doc = "Field `CPU_INTR_FROM_CPU_1` reader - Set 1 to generate cpu interrupt 1"]
+pub type CPU_INTR_FROM_CPU_1_R = crate::BitReader;
+#[doc = "Field `CPU_INTR_FROM_CPU_1` writer - Set 1 to generate cpu interrupt 1"]
+pub type CPU_INTR_FROM_CPU_1_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 1"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_1(&self) -> CPU_INTR_FROM_CPU_1_R {
+        CPU_INTR_FROM_CPU_1_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_INTR_FROM_CPU_1")
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 1"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_1(&mut self) -> CPU_INTR_FROM_CPU_1_W<CPU_INTR_FROM_CPU_1_SPEC> {
+        CPU_INTR_FROM_CPU_1_W::new(self, 0)
+    }
+}
+#[doc = "interrupt source register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_INTR_FROM_CPU_1_SPEC;
+impl crate::RegisterSpec for CPU_INTR_FROM_CPU_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_intr_from_cpu_1::R`](R) reader structure"]
+impl crate::Readable for CPU_INTR_FROM_CPU_1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_intr_from_cpu_1::W`](W) writer structure"]
+impl crate::Writable for CPU_INTR_FROM_CPU_1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_INTR_FROM_CPU_1 to value 0"]
+impl crate::Resettable for CPU_INTR_FROM_CPU_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/cpu_intr_from_cpu_2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CPU_INTR_FROM_CPU_2` reader"]
+pub type R = crate::R<CPU_INTR_FROM_CPU_2_SPEC>;
+#[doc = "Register `CPU_INTR_FROM_CPU_2` writer"]
+pub type W = crate::W<CPU_INTR_FROM_CPU_2_SPEC>;
+#[doc = "Field `CPU_INTR_FROM_CPU_2` reader - Set 1 to generate cpu interrupt 2"]
+pub type CPU_INTR_FROM_CPU_2_R = crate::BitReader;
+#[doc = "Field `CPU_INTR_FROM_CPU_2` writer - Set 1 to generate cpu interrupt 2"]
+pub type CPU_INTR_FROM_CPU_2_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 2"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_2(&self) -> CPU_INTR_FROM_CPU_2_R {
+        CPU_INTR_FROM_CPU_2_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_INTR_FROM_CPU_2")
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 2"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_2(&mut self) -> CPU_INTR_FROM_CPU_2_W<CPU_INTR_FROM_CPU_2_SPEC> {
+        CPU_INTR_FROM_CPU_2_W::new(self, 0)
+    }
+}
+#[doc = "interrupt source register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_INTR_FROM_CPU_2_SPEC;
+impl crate::RegisterSpec for CPU_INTR_FROM_CPU_2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_intr_from_cpu_2::R`](R) reader structure"]
+impl crate::Readable for CPU_INTR_FROM_CPU_2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_intr_from_cpu_2::W`](W) writer structure"]
+impl crate::Writable for CPU_INTR_FROM_CPU_2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_INTR_FROM_CPU_2 to value 0"]
+impl crate::Resettable for CPU_INTR_FROM_CPU_2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/cpu_intr_from_cpu_3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CPU_INTR_FROM_CPU_3` reader"]
+pub type R = crate::R<CPU_INTR_FROM_CPU_3_SPEC>;
+#[doc = "Register `CPU_INTR_FROM_CPU_3` writer"]
+pub type W = crate::W<CPU_INTR_FROM_CPU_3_SPEC>;
+#[doc = "Field `CPU_INTR_FROM_CPU_3` reader - Set 1 to generate cpu interrupt 3"]
+pub type CPU_INTR_FROM_CPU_3_R = crate::BitReader;
+#[doc = "Field `CPU_INTR_FROM_CPU_3` writer - Set 1 to generate cpu interrupt 3"]
+pub type CPU_INTR_FROM_CPU_3_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 3"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_3(&self) -> CPU_INTR_FROM_CPU_3_R {
+        CPU_INTR_FROM_CPU_3_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_INTR_FROM_CPU_3")
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to generate cpu interrupt 3"]
+    #[inline(always)]
+    pub fn cpu_intr_from_cpu_3(&mut self) -> CPU_INTR_FROM_CPU_3_W<CPU_INTR_FROM_CPU_3_SPEC> {
+        CPU_INTR_FROM_CPU_3_W::new(self, 0)
+    }
+}
+#[doc = "interrupt source register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_INTR_FROM_CPU_3_SPEC;
+impl crate::RegisterSpec for CPU_INTR_FROM_CPU_3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_intr_from_cpu_3::R`](R) reader structure"]
+impl crate::Readable for CPU_INTR_FROM_CPU_3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_intr_from_cpu_3::W`](W) writer structure"]
+impl crate::Writable for CPU_INTR_FROM_CPU_3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_INTR_FROM_CPU_3 to value 0"]
+impl crate::Resettable for CPU_INTR_FROM_CPU_3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/cpu_per_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `CPU_PER_CONF` reader"]
+pub type R = crate::R<CPU_PER_CONF_SPEC>;
+#[doc = "Register `CPU_PER_CONF` writer"]
+pub type W = crate::W<CPU_PER_CONF_SPEC>;
+#[doc = "Field `CPUPERIOD_SEL` reader - This field used to sel cpu clock frequent."]
+pub type CPUPERIOD_SEL_R = crate::FieldReader;
+#[doc = "Field `CPUPERIOD_SEL` writer - This field used to sel cpu clock frequent."]
+pub type CPUPERIOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `PLL_FREQ_SEL` reader - This field used to sel pll frequent."]
+pub type PLL_FREQ_SEL_R = crate::BitReader;
+#[doc = "Field `PLL_FREQ_SEL` writer - This field used to sel pll frequent."]
+pub type PLL_FREQ_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_WAIT_MODE_FORCE_ON` reader - Set 1 to force cpu_waiti_clk enable."]
+pub type CPU_WAIT_MODE_FORCE_ON_R = crate::BitReader;
+#[doc = "Field `CPU_WAIT_MODE_FORCE_ON` writer - Set 1 to force cpu_waiti_clk enable."]
+pub type CPU_WAIT_MODE_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_WAITI_DELAY_NUM` reader - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
+pub type CPU_WAITI_DELAY_NUM_R = crate::FieldReader;
+#[doc = "Field `CPU_WAITI_DELAY_NUM` writer - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
+pub type CPU_WAITI_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:1 - This field used to sel cpu clock frequent."]
+    #[inline(always)]
+    pub fn cpuperiod_sel(&self) -> CPUPERIOD_SEL_R {
+        CPUPERIOD_SEL_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 2 - This field used to sel pll frequent."]
+    #[inline(always)]
+    pub fn pll_freq_sel(&self) -> PLL_FREQ_SEL_R {
+        PLL_FREQ_SEL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to force cpu_waiti_clk enable."]
+    #[inline(always)]
+    pub fn cpu_wait_mode_force_on(&self) -> CPU_WAIT_MODE_FORCE_ON_R {
+        CPU_WAIT_MODE_FORCE_ON_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:7 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
+    #[inline(always)]
+    pub fn cpu_waiti_delay_num(&self) -> CPU_WAITI_DELAY_NUM_R {
+        CPU_WAITI_DELAY_NUM_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_PER_CONF")
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - This field used to sel cpu clock frequent."]
+    #[inline(always)]
+    pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PER_CONF_SPEC> {
+        CPUPERIOD_SEL_W::new(self, 0)
+    }
+    #[doc = "Bit 2 - This field used to sel pll frequent."]
+    #[inline(always)]
+    pub fn pll_freq_sel(&mut self) -> PLL_FREQ_SEL_W<CPU_PER_CONF_SPEC> {
+        PLL_FREQ_SEL_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to force cpu_waiti_clk enable."]
+    #[inline(always)]
+    pub fn cpu_wait_mode_force_on(&mut self) -> CPU_WAIT_MODE_FORCE_ON_W<CPU_PER_CONF_SPEC> {
+        CPU_WAIT_MODE_FORCE_ON_W::new(self, 3)
+    }
+    #[doc = "Bits 4:7 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
+    #[inline(always)]
+    pub fn cpu_waiti_delay_num(&mut self) -> CPU_WAITI_DELAY_NUM_W<CPU_PER_CONF_SPEC> {
+        CPU_WAITI_DELAY_NUM_W::new(self, 4)
+    }
+}
+#[doc = "cpu peripheral clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_per_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_per_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_PER_CONF_SPEC;
+impl crate::RegisterSpec for CPU_PER_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_per_conf::R`](R) reader structure"]
+impl crate::Readable for CPU_PER_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_per_conf::W`](W) writer structure"]
+impl crate::Writable for CPU_PER_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_PER_CONF to value 0x0c"]
+impl crate::Resettable for CPU_PER_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0c;
+}

vendor/esp32s3/src/system/cpu_peri_clk_en.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CPU_PERI_CLK_EN` reader"]
+pub type R = crate::R<CPU_PERI_CLK_EN_SPEC>;
+#[doc = "Register `CPU_PERI_CLK_EN` writer"]
+pub type W = crate::W<CPU_PERI_CLK_EN_SPEC>;
+#[doc = "Field `CLK_EN_ASSIST_DEBUG` reader - Set 1 to open assist_debug module clock"]
+pub type CLK_EN_ASSIST_DEBUG_R = crate::BitReader;
+#[doc = "Field `CLK_EN_ASSIST_DEBUG` writer - Set 1 to open assist_debug module clock"]
+pub type CLK_EN_ASSIST_DEBUG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_EN_DEDICATED_GPIO` reader - Set 1 to open dedicated_gpio module clk"]
+pub type CLK_EN_DEDICATED_GPIO_R = crate::BitReader;
+#[doc = "Field `CLK_EN_DEDICATED_GPIO` writer - Set 1 to open dedicated_gpio module clk"]
+pub type CLK_EN_DEDICATED_GPIO_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 6 - Set 1 to open assist_debug module clock"]
+    #[inline(always)]
+    pub fn clk_en_assist_debug(&self) -> CLK_EN_ASSIST_DEBUG_R {
+        CLK_EN_ASSIST_DEBUG_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set 1 to open dedicated_gpio module clk"]
+    #[inline(always)]
+    pub fn clk_en_dedicated_gpio(&self) -> CLK_EN_DEDICATED_GPIO_R {
+        CLK_EN_DEDICATED_GPIO_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_PERI_CLK_EN")
+            .field("clk_en_assist_debug", &self.clk_en_assist_debug())
+            .field("clk_en_dedicated_gpio", &self.clk_en_dedicated_gpio())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 6 - Set 1 to open assist_debug module clock"]
+    #[inline(always)]
+    pub fn clk_en_assist_debug(&mut self) -> CLK_EN_ASSIST_DEBUG_W<CPU_PERI_CLK_EN_SPEC> {
+        CLK_EN_ASSIST_DEBUG_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set 1 to open dedicated_gpio module clk"]
+    #[inline(always)]
+    pub fn clk_en_dedicated_gpio(&mut self) -> CLK_EN_DEDICATED_GPIO_W<CPU_PERI_CLK_EN_SPEC> {
+        CLK_EN_DEDICATED_GPIO_W::new(self, 7)
+    }
+}
+#[doc = "cpu_peripheral clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_peri_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_peri_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_PERI_CLK_EN_SPEC;
+impl crate::RegisterSpec for CPU_PERI_CLK_EN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_peri_clk_en::R`](R) reader structure"]
+impl crate::Readable for CPU_PERI_CLK_EN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_peri_clk_en::W`](W) writer structure"]
+impl crate::Writable for CPU_PERI_CLK_EN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_PERI_CLK_EN to value 0"]
+impl crate::Resettable for CPU_PERI_CLK_EN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/cpu_peri_rst_en.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CPU_PERI_RST_EN` reader"]
+pub type R = crate::R<CPU_PERI_RST_EN_SPEC>;
+#[doc = "Register `CPU_PERI_RST_EN` writer"]
+pub type W = crate::W<CPU_PERI_RST_EN_SPEC>;
+#[doc = "Field `RST_EN_ASSIST_DEBUG` reader - Set 1 to let assist_debug module reset"]
+pub type RST_EN_ASSIST_DEBUG_R = crate::BitReader;
+#[doc = "Field `RST_EN_ASSIST_DEBUG` writer - Set 1 to let assist_debug module reset"]
+pub type RST_EN_ASSIST_DEBUG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RST_EN_DEDICATED_GPIO` reader - Set 1 to let dedicated_gpio module reset"]
+pub type RST_EN_DEDICATED_GPIO_R = crate::BitReader;
+#[doc = "Field `RST_EN_DEDICATED_GPIO` writer - Set 1 to let dedicated_gpio module reset"]
+pub type RST_EN_DEDICATED_GPIO_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 6 - Set 1 to let assist_debug module reset"]
+    #[inline(always)]
+    pub fn rst_en_assist_debug(&self) -> RST_EN_ASSIST_DEBUG_R {
+        RST_EN_ASSIST_DEBUG_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set 1 to let dedicated_gpio module reset"]
+    #[inline(always)]
+    pub fn rst_en_dedicated_gpio(&self) -> RST_EN_DEDICATED_GPIO_R {
+        RST_EN_DEDICATED_GPIO_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_PERI_RST_EN")
+            .field("rst_en_assist_debug", &self.rst_en_assist_debug())
+            .field("rst_en_dedicated_gpio", &self.rst_en_dedicated_gpio())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 6 - Set 1 to let assist_debug module reset"]
+    #[inline(always)]
+    pub fn rst_en_assist_debug(&mut self) -> RST_EN_ASSIST_DEBUG_W<CPU_PERI_RST_EN_SPEC> {
+        RST_EN_ASSIST_DEBUG_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set 1 to let dedicated_gpio module reset"]
+    #[inline(always)]
+    pub fn rst_en_dedicated_gpio(&mut self) -> RST_EN_DEDICATED_GPIO_W<CPU_PERI_RST_EN_SPEC> {
+        RST_EN_DEDICATED_GPIO_W::new(self, 7)
+    }
+}
+#[doc = "cpu_peripheral reset configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_peri_rst_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_peri_rst_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_PERI_RST_EN_SPEC;
+impl crate::RegisterSpec for CPU_PERI_RST_EN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_peri_rst_en::R`](R) reader structure"]
+impl crate::Readable for CPU_PERI_RST_EN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_peri_rst_en::W`](W) writer structure"]
+impl crate::Writable for CPU_PERI_RST_EN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_PERI_RST_EN to value 0xc0"]
+impl crate::Resettable for CPU_PERI_RST_EN_SPEC {
+    const RESET_VALUE: u32 = 0xc0;
+}

vendor/esp32s3/src/system/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - version register"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - version register"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - version register"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - version register"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0210_1220"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0210_1220;
+}

vendor/esp32s3/src/system/edma_ctrl.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `EDMA_CTRL` reader"]
+pub type R = crate::R<EDMA_CTRL_SPEC>;
+#[doc = "Register `EDMA_CTRL` writer"]
+pub type W = crate::W<EDMA_CTRL_SPEC>;
+#[doc = "Field `EDMA_CLK_ON` reader - Set 1 to enable EDMA clock."]
+pub type EDMA_CLK_ON_R = crate::BitReader;
+#[doc = "Field `EDMA_CLK_ON` writer - Set 1 to enable EDMA clock."]
+pub type EDMA_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EDMA_RESET` reader - Set 1 to let EDMA reset"]
+pub type EDMA_RESET_R = crate::BitReader;
+#[doc = "Field `EDMA_RESET` writer - Set 1 to let EDMA reset"]
+pub type EDMA_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to enable EDMA clock."]
+    #[inline(always)]
+    pub fn edma_clk_on(&self) -> EDMA_CLK_ON_R {
+        EDMA_CLK_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let EDMA reset"]
+    #[inline(always)]
+    pub fn edma_reset(&self) -> EDMA_RESET_R {
+        EDMA_RESET_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EDMA_CTRL")
+            .field("edma_clk_on", &self.edma_clk_on())
+            .field("edma_reset", &self.edma_reset())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to enable EDMA clock."]
+    #[inline(always)]
+    pub fn edma_clk_on(&mut self) -> EDMA_CLK_ON_W<EDMA_CTRL_SPEC> {
+        EDMA_CLK_ON_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let EDMA reset"]
+    #[inline(always)]
+    pub fn edma_reset(&mut self) -> EDMA_RESET_W<EDMA_CTRL_SPEC> {
+        EDMA_RESET_W::new(self, 1)
+    }
+}
+#[doc = "EDMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`edma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EDMA_CTRL_SPEC;
+impl crate::RegisterSpec for EDMA_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`edma_ctrl::R`](R) reader structure"]
+impl crate::Readable for EDMA_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`edma_ctrl::W`](W) writer structure"]
+impl crate::Writable for EDMA_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EDMA_CTRL to value 0x01"]
+impl crate::Resettable for EDMA_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/system/external_device_encrypt_decrypt_control.rs

@@ -0,0 +1,112 @@
+#[doc = "Register `EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL` reader"]
+pub type R = crate::R<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC>;
+#[doc = "Register `EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL` writer"]
+pub type W = crate::W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC>;
+#[doc = "Field `ENABLE_SPI_MANUAL_ENCRYPT` reader - Set 1 to enable the SPI manual encrypt."]
+pub type ENABLE_SPI_MANUAL_ENCRYPT_R = crate::BitReader;
+#[doc = "Field `ENABLE_SPI_MANUAL_ENCRYPT` writer - Set 1 to enable the SPI manual encrypt."]
+pub type ENABLE_SPI_MANUAL_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLE_DOWNLOAD_DB_ENCRYPT` reader - Set 1 to enable download DB encrypt."]
+pub type ENABLE_DOWNLOAD_DB_ENCRYPT_R = crate::BitReader;
+#[doc = "Field `ENABLE_DOWNLOAD_DB_ENCRYPT` writer - Set 1 to enable download DB encrypt."]
+pub type ENABLE_DOWNLOAD_DB_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLE_DOWNLOAD_G0CB_DECRYPT` reader - Set 1 to enable download G0CB decrypt"]
+pub type ENABLE_DOWNLOAD_G0CB_DECRYPT_R = crate::BitReader;
+#[doc = "Field `ENABLE_DOWNLOAD_G0CB_DECRYPT` writer - Set 1 to enable download G0CB decrypt"]
+pub type ENABLE_DOWNLOAD_G0CB_DECRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENABLE_DOWNLOAD_MANUAL_ENCRYPT` reader - Set 1 to enable download manual encrypt"]
+pub type ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R = crate::BitReader;
+#[doc = "Field `ENABLE_DOWNLOAD_MANUAL_ENCRYPT` writer - Set 1 to enable download manual encrypt"]
+pub type ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to enable the SPI manual encrypt."]
+    #[inline(always)]
+    pub fn enable_spi_manual_encrypt(&self) -> ENABLE_SPI_MANUAL_ENCRYPT_R {
+        ENABLE_SPI_MANUAL_ENCRYPT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to enable download DB encrypt."]
+    #[inline(always)]
+    pub fn enable_download_db_encrypt(&self) -> ENABLE_DOWNLOAD_DB_ENCRYPT_R {
+        ENABLE_DOWNLOAD_DB_ENCRYPT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to enable download G0CB decrypt"]
+    #[inline(always)]
+    pub fn enable_download_g0cb_decrypt(&self) -> ENABLE_DOWNLOAD_G0CB_DECRYPT_R {
+        ENABLE_DOWNLOAD_G0CB_DECRYPT_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to enable download manual encrypt"]
+    #[inline(always)]
+    pub fn enable_download_manual_encrypt(&self) -> ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R {
+        ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
+            .field(
+                "enable_spi_manual_encrypt",
+                &self.enable_spi_manual_encrypt(),
+            )
+            .field(
+                "enable_download_db_encrypt",
+                &self.enable_download_db_encrypt(),
+            )
+            .field(
+                "enable_download_g0cb_decrypt",
+                &self.enable_download_g0cb_decrypt(),
+            )
+            .field(
+                "enable_download_manual_encrypt",
+                &self.enable_download_manual_encrypt(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to enable the SPI manual encrypt."]
+    #[inline(always)]
+    pub fn enable_spi_manual_encrypt(
+        &mut self,
+    ) -> ENABLE_SPI_MANUAL_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
+        ENABLE_SPI_MANUAL_ENCRYPT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to enable download DB encrypt."]
+    #[inline(always)]
+    pub fn enable_download_db_encrypt(
+        &mut self,
+    ) -> ENABLE_DOWNLOAD_DB_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
+        ENABLE_DOWNLOAD_DB_ENCRYPT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to enable download G0CB decrypt"]
+    #[inline(always)]
+    pub fn enable_download_g0cb_decrypt(
+        &mut self,
+    ) -> ENABLE_DOWNLOAD_G0CB_DECRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
+        ENABLE_DOWNLOAD_G0CB_DECRYPT_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to enable download manual encrypt"]
+    #[inline(always)]
+    pub fn enable_download_manual_encrypt(
+        &mut self,
+    ) -> ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
+        ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W::new(self, 3)
+    }
+}
+#[doc = "External memory encrypt and decrypt control register\n\nYou can [`read`](crate::Reg::read) this register and get [`external_device_encrypt_decrypt_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`external_device_encrypt_decrypt_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC;
+impl crate::RegisterSpec for EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`external_device_encrypt_decrypt_control::R`](R) reader structure"]
+impl crate::Readable for EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`external_device_encrypt_decrypt_control::W`](W) writer structure"]
+impl crate::Writable for EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL to value 0"]
+impl crate::Resettable for EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/mem_pd_mask.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `MEM_PD_MASK` reader"]
+pub type R = crate::R<MEM_PD_MASK_SPEC>;
+#[doc = "Register `MEM_PD_MASK` writer"]
+pub type W = crate::W<MEM_PD_MASK_SPEC>;
+#[doc = "Field `LSLP_MEM_PD_MASK` reader - Set 1 to mask memory power down."]
+pub type LSLP_MEM_PD_MASK_R = crate::BitReader;
+#[doc = "Field `LSLP_MEM_PD_MASK` writer - Set 1 to mask memory power down."]
+pub type LSLP_MEM_PD_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to mask memory power down."]
+    #[inline(always)]
+    pub fn lslp_mem_pd_mask(&self) -> LSLP_MEM_PD_MASK_R {
+        LSLP_MEM_PD_MASK_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MEM_PD_MASK")
+            .field("lslp_mem_pd_mask", &self.lslp_mem_pd_mask())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to mask memory power down."]
+    #[inline(always)]
+    pub fn lslp_mem_pd_mask(&mut self) -> LSLP_MEM_PD_MASK_W<MEM_PD_MASK_SPEC> {
+        LSLP_MEM_PD_MASK_W::new(self, 0)
+    }
+}
+#[doc = "memory power down mask configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_pd_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_pd_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MEM_PD_MASK_SPEC;
+impl crate::RegisterSpec for MEM_PD_MASK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mem_pd_mask::R`](R) reader structure"]
+impl crate::Readable for MEM_PD_MASK_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mem_pd_mask::W`](W) writer structure"]
+impl crate::Writable for MEM_PD_MASK_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MEM_PD_MASK to value 0x01"]
+impl crate::Resettable for MEM_PD_MASK_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/system/mem_pvt.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `MEM_PVT` reader"]
+pub type R = crate::R<MEM_PVT_SPEC>;
+#[doc = "Register `MEM_PVT` writer"]
+pub type W = crate::W<MEM_PVT_SPEC>;
+#[doc = "Field `MEM_PATH_LEN` reader - ******* Description ***********"]
+pub type MEM_PATH_LEN_R = crate::FieldReader;
+#[doc = "Field `MEM_PATH_LEN` writer - ******* Description ***********"]
+pub type MEM_PATH_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `MEM_ERR_CNT_CLR` writer - ******* Description ***********"]
+pub type MEM_ERR_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MONITOR_EN` reader - ******* Description ***********"]
+pub type MONITOR_EN_R = crate::BitReader;
+#[doc = "Field `MONITOR_EN` writer - ******* Description ***********"]
+pub type MONITOR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEM_TIMING_ERR_CNT` reader - ******* Description ***********"]
+pub type MEM_TIMING_ERR_CNT_R = crate::FieldReader<u16>;
+#[doc = "Field `MEM_VT_SEL` reader - ******* Description ***********"]
+pub type MEM_VT_SEL_R = crate::FieldReader;
+#[doc = "Field `MEM_VT_SEL` writer - ******* Description ***********"]
+pub type MEM_VT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:3 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn mem_path_len(&self) -> MEM_PATH_LEN_R {
+        MEM_PATH_LEN_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 5 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn monitor_en(&self) -> MONITOR_EN_R {
+        MONITOR_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bits 6:21 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn mem_timing_err_cnt(&self) -> MEM_TIMING_ERR_CNT_R {
+        MEM_TIMING_ERR_CNT_R::new(((self.bits >> 6) & 0xffff) as u16)
+    }
+    #[doc = "Bits 22:23 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn mem_vt_sel(&self) -> MEM_VT_SEL_R {
+        MEM_VT_SEL_R::new(((self.bits >> 22) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MEM_PVT")
+            .field("mem_path_len", &self.mem_path_len())
+            .field("monitor_en", &self.monitor_en())
+            .field("mem_timing_err_cnt", &self.mem_timing_err_cnt())
+            .field("mem_vt_sel", &self.mem_vt_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn mem_path_len(&mut self) -> MEM_PATH_LEN_W<MEM_PVT_SPEC> {
+        MEM_PATH_LEN_W::new(self, 0)
+    }
+    #[doc = "Bit 4 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn mem_err_cnt_clr(&mut self) -> MEM_ERR_CNT_CLR_W<MEM_PVT_SPEC> {
+        MEM_ERR_CNT_CLR_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn monitor_en(&mut self) -> MONITOR_EN_W<MEM_PVT_SPEC> {
+        MONITOR_EN_W::new(self, 5)
+    }
+    #[doc = "Bits 22:23 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn mem_vt_sel(&mut self) -> MEM_VT_SEL_W<MEM_PVT_SPEC> {
+        MEM_VT_SEL_W::new(self, 22)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_pvt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_pvt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MEM_PVT_SPEC;
+impl crate::RegisterSpec for MEM_PVT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mem_pvt::R`](R) reader structure"]
+impl crate::Readable for MEM_PVT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mem_pvt::W`](W) writer structure"]
+impl crate::Writable for MEM_PVT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MEM_PVT to value 0x03"]
+impl crate::Resettable for MEM_PVT_SPEC {
+    const RESET_VALUE: u32 = 0x03;
+}

vendor/esp32s3/src/system/perip_clk_en0.rs

@@ -0,0 +1,512 @@
+#[doc = "Register `PERIP_CLK_EN0` reader"]
+pub type R = crate::R<PERIP_CLK_EN0_SPEC>;
+#[doc = "Register `PERIP_CLK_EN0` writer"]
+pub type W = crate::W<PERIP_CLK_EN0_SPEC>;
+#[doc = "Field `TIMERS_CLK_EN` reader - Set 1 to enable TIMERS clock"]
+pub type TIMERS_CLK_EN_R = crate::BitReader;
+#[doc = "Field `TIMERS_CLK_EN` writer - Set 1 to enable TIMERS clock"]
+pub type TIMERS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI01_CLK_EN` reader - Set 1 to enable SPI01 clock"]
+pub type SPI01_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SPI01_CLK_EN` writer - Set 1 to enable SPI01 clock"]
+pub type SPI01_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_CLK_EN` reader - Set 1 to enable UART clock"]
+pub type UART_CLK_EN_R = crate::BitReader;
+#[doc = "Field `UART_CLK_EN` writer - Set 1 to enable UART clock"]
+pub type UART_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDG_CLK_EN` reader - Set 1 to enable WDG clock"]
+pub type WDG_CLK_EN_R = crate::BitReader;
+#[doc = "Field `WDG_CLK_EN` writer - Set 1 to enable WDG clock"]
+pub type WDG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2S0_CLK_EN` reader - Set 1 to enable I2S0 clock"]
+pub type I2S0_CLK_EN_R = crate::BitReader;
+#[doc = "Field `I2S0_CLK_EN` writer - Set 1 to enable I2S0 clock"]
+pub type I2S0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART1_CLK_EN` reader - Set 1 to enable UART1 clock"]
+pub type UART1_CLK_EN_R = crate::BitReader;
+#[doc = "Field `UART1_CLK_EN` writer - Set 1 to enable UART1 clock"]
+pub type UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI2_CLK_EN` reader - Set 1 to enable SPI2 clock"]
+pub type SPI2_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SPI2_CLK_EN` writer - Set 1 to enable SPI2 clock"]
+pub type SPI2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_EXT0_CLK_EN` reader - Set 1 to enable I2C_EXT0 clock"]
+pub type I2C_EXT0_CLK_EN_R = crate::BitReader;
+#[doc = "Field `I2C_EXT0_CLK_EN` writer - Set 1 to enable I2C_EXT0 clock"]
+pub type I2C_EXT0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UHCI0_CLK_EN` reader - Set 1 to enable UHCI0 clock"]
+pub type UHCI0_CLK_EN_R = crate::BitReader;
+#[doc = "Field `UHCI0_CLK_EN` writer - Set 1 to enable UHCI0 clock"]
+pub type UHCI0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RMT_CLK_EN` reader - Set 1 to enable RMT clock"]
+pub type RMT_CLK_EN_R = crate::BitReader;
+#[doc = "Field `RMT_CLK_EN` writer - Set 1 to enable RMT clock"]
+pub type RMT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PCNT_CLK_EN` reader - Set 1 to enable PCNT clock"]
+pub type PCNT_CLK_EN_R = crate::BitReader;
+#[doc = "Field `PCNT_CLK_EN` writer - Set 1 to enable PCNT clock"]
+pub type PCNT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LEDC_CLK_EN` reader - Set 1 to enable LEDC clock"]
+pub type LEDC_CLK_EN_R = crate::BitReader;
+#[doc = "Field `LEDC_CLK_EN` writer - Set 1 to enable LEDC clock"]
+pub type LEDC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UHCI1_CLK_EN` reader - Set 1 to enable UHCI1 clock"]
+pub type UHCI1_CLK_EN_R = crate::BitReader;
+#[doc = "Field `UHCI1_CLK_EN` writer - Set 1 to enable UHCI1 clock"]
+pub type UHCI1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMERGROUP_CLK_EN` reader - Set 1 to enable TIMERGROUP clock"]
+pub type TIMERGROUP_CLK_EN_R = crate::BitReader;
+#[doc = "Field `TIMERGROUP_CLK_EN` writer - Set 1 to enable TIMERGROUP clock"]
+pub type TIMERGROUP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EFUSE_CLK_EN` reader - Set 1 to enable EFUSE clock"]
+pub type EFUSE_CLK_EN_R = crate::BitReader;
+#[doc = "Field `EFUSE_CLK_EN` writer - Set 1 to enable EFUSE clock"]
+pub type EFUSE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMERGROUP1_CLK_EN` reader - Set 1 to enable TIMERGROUP1 clock"]
+pub type TIMERGROUP1_CLK_EN_R = crate::BitReader;
+#[doc = "Field `TIMERGROUP1_CLK_EN` writer - Set 1 to enable TIMERGROUP1 clock"]
+pub type TIMERGROUP1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI3_CLK_EN` reader - Set 1 to enable SPI3 clock"]
+pub type SPI3_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SPI3_CLK_EN` writer - Set 1 to enable SPI3 clock"]
+pub type SPI3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM0_CLK_EN` reader - Set 1 to enable PWM0 clock"]
+pub type PWM0_CLK_EN_R = crate::BitReader;
+#[doc = "Field `PWM0_CLK_EN` writer - Set 1 to enable PWM0 clock"]
+pub type PWM0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_EXT1_CLK_EN` reader - Set 1 to enable I2C_EXT1 clock"]
+pub type I2C_EXT1_CLK_EN_R = crate::BitReader;
+#[doc = "Field `I2C_EXT1_CLK_EN` writer - Set 1 to enable I2C_EXT1 clock"]
+pub type I2C_EXT1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TWAI_CLK_EN` reader - Set 1 to enable CAN clock"]
+pub type TWAI_CLK_EN_R = crate::BitReader;
+#[doc = "Field `TWAI_CLK_EN` writer - Set 1 to enable CAN clock"]
+pub type TWAI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM1_CLK_EN` reader - Set 1 to enable PWM1 clock"]
+pub type PWM1_CLK_EN_R = crate::BitReader;
+#[doc = "Field `PWM1_CLK_EN` writer - Set 1 to enable PWM1 clock"]
+pub type PWM1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2S1_CLK_EN` reader - Set 1 to enable I2S1 clock"]
+pub type I2S1_CLK_EN_R = crate::BitReader;
+#[doc = "Field `I2S1_CLK_EN` writer - Set 1 to enable I2S1 clock"]
+pub type I2S1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI2_DMA_CLK_EN` reader - Set 1 to enable SPI2_DMA clock"]
+pub type SPI2_DMA_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SPI2_DMA_CLK_EN` writer - Set 1 to enable SPI2_DMA clock"]
+pub type SPI2_DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_CLK_EN` reader - Set 1 to enable USB clock"]
+pub type USB_CLK_EN_R = crate::BitReader;
+#[doc = "Field `USB_CLK_EN` writer - Set 1 to enable USB clock"]
+pub type USB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_MEM_CLK_EN` reader - Set 1 to enable UART_MEM clock"]
+pub type UART_MEM_CLK_EN_R = crate::BitReader;
+#[doc = "Field `UART_MEM_CLK_EN` writer - Set 1 to enable UART_MEM clock"]
+pub type UART_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM2_CLK_EN` reader - Set 1 to enable PWM2 clock"]
+pub type PWM2_CLK_EN_R = crate::BitReader;
+#[doc = "Field `PWM2_CLK_EN` writer - Set 1 to enable PWM2 clock"]
+pub type PWM2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM3_CLK_EN` reader - Set 1 to enable PWM3 clock"]
+pub type PWM3_CLK_EN_R = crate::BitReader;
+#[doc = "Field `PWM3_CLK_EN` writer - Set 1 to enable PWM3 clock"]
+pub type PWM3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI3_DMA_CLK_EN` reader - Set 1 to enable SPI4 clock"]
+pub type SPI3_DMA_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SPI3_DMA_CLK_EN` writer - Set 1 to enable SPI4 clock"]
+pub type SPI3_DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APB_SARADC_CLK_EN` reader - Set 1 to enable APB_SARADC clock"]
+pub type APB_SARADC_CLK_EN_R = crate::BitReader;
+#[doc = "Field `APB_SARADC_CLK_EN` writer - Set 1 to enable APB_SARADC clock"]
+pub type APB_SARADC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SYSTIMER_CLK_EN` reader - Set 1 to enable SYSTEMTIMER clock"]
+pub type SYSTIMER_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SYSTIMER_CLK_EN` writer - Set 1 to enable SYSTEMTIMER clock"]
+pub type SYSTIMER_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC2_ARB_CLK_EN` reader - Set 1 to enable ADC2_ARB clock"]
+pub type ADC2_ARB_CLK_EN_R = crate::BitReader;
+#[doc = "Field `ADC2_ARB_CLK_EN` writer - Set 1 to enable ADC2_ARB clock"]
+pub type ADC2_ARB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI4_CLK_EN` reader - Set 1 to enable SPI4 clock"]
+pub type SPI4_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SPI4_CLK_EN` writer - Set 1 to enable SPI4 clock"]
+pub type SPI4_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to enable TIMERS clock"]
+    #[inline(always)]
+    pub fn timers_clk_en(&self) -> TIMERS_CLK_EN_R {
+        TIMERS_CLK_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to enable SPI01 clock"]
+    #[inline(always)]
+    pub fn spi01_clk_en(&self) -> SPI01_CLK_EN_R {
+        SPI01_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to enable UART clock"]
+    #[inline(always)]
+    pub fn uart_clk_en(&self) -> UART_CLK_EN_R {
+        UART_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to enable WDG clock"]
+    #[inline(always)]
+    pub fn wdg_clk_en(&self) -> WDG_CLK_EN_R {
+        WDG_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set 1 to enable I2S0 clock"]
+    #[inline(always)]
+    pub fn i2s0_clk_en(&self) -> I2S0_CLK_EN_R {
+        I2S0_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set 1 to enable UART1 clock"]
+    #[inline(always)]
+    pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R {
+        UART1_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set 1 to enable SPI2 clock"]
+    #[inline(always)]
+    pub fn spi2_clk_en(&self) -> SPI2_CLK_EN_R {
+        SPI2_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set 1 to enable I2C_EXT0 clock"]
+    #[inline(always)]
+    pub fn i2c_ext0_clk_en(&self) -> I2C_EXT0_CLK_EN_R {
+        I2C_EXT0_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set 1 to enable UHCI0 clock"]
+    #[inline(always)]
+    pub fn uhci0_clk_en(&self) -> UHCI0_CLK_EN_R {
+        UHCI0_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Set 1 to enable RMT clock"]
+    #[inline(always)]
+    pub fn rmt_clk_en(&self) -> RMT_CLK_EN_R {
+        RMT_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Set 1 to enable PCNT clock"]
+    #[inline(always)]
+    pub fn pcnt_clk_en(&self) -> PCNT_CLK_EN_R {
+        PCNT_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Set 1 to enable LEDC clock"]
+    #[inline(always)]
+    pub fn ledc_clk_en(&self) -> LEDC_CLK_EN_R {
+        LEDC_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Set 1 to enable UHCI1 clock"]
+    #[inline(always)]
+    pub fn uhci1_clk_en(&self) -> UHCI1_CLK_EN_R {
+        UHCI1_CLK_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Set 1 to enable TIMERGROUP clock"]
+    #[inline(always)]
+    pub fn timergroup_clk_en(&self) -> TIMERGROUP_CLK_EN_R {
+        TIMERGROUP_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - Set 1 to enable EFUSE clock"]
+    #[inline(always)]
+    pub fn efuse_clk_en(&self) -> EFUSE_CLK_EN_R {
+        EFUSE_CLK_EN_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Set 1 to enable TIMERGROUP1 clock"]
+    #[inline(always)]
+    pub fn timergroup1_clk_en(&self) -> TIMERGROUP1_CLK_EN_R {
+        TIMERGROUP1_CLK_EN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Set 1 to enable SPI3 clock"]
+    #[inline(always)]
+    pub fn spi3_clk_en(&self) -> SPI3_CLK_EN_R {
+        SPI3_CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Set 1 to enable PWM0 clock"]
+    #[inline(always)]
+    pub fn pwm0_clk_en(&self) -> PWM0_CLK_EN_R {
+        PWM0_CLK_EN_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Set 1 to enable I2C_EXT1 clock"]
+    #[inline(always)]
+    pub fn i2c_ext1_clk_en(&self) -> I2C_EXT1_CLK_EN_R {
+        I2C_EXT1_CLK_EN_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Set 1 to enable CAN clock"]
+    #[inline(always)]
+    pub fn twai_clk_en(&self) -> TWAI_CLK_EN_R {
+        TWAI_CLK_EN_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - Set 1 to enable PWM1 clock"]
+    #[inline(always)]
+    pub fn pwm1_clk_en(&self) -> PWM1_CLK_EN_R {
+        PWM1_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Set 1 to enable I2S1 clock"]
+    #[inline(always)]
+    pub fn i2s1_clk_en(&self) -> I2S1_CLK_EN_R {
+        I2S1_CLK_EN_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Set 1 to enable SPI2_DMA clock"]
+    #[inline(always)]
+    pub fn spi2_dma_clk_en(&self) -> SPI2_DMA_CLK_EN_R {
+        SPI2_DMA_CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Set 1 to enable USB clock"]
+    #[inline(always)]
+    pub fn usb_clk_en(&self) -> USB_CLK_EN_R {
+        USB_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Set 1 to enable UART_MEM clock"]
+    #[inline(always)]
+    pub fn uart_mem_clk_en(&self) -> UART_MEM_CLK_EN_R {
+        UART_MEM_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - Set 1 to enable PWM2 clock"]
+    #[inline(always)]
+    pub fn pwm2_clk_en(&self) -> PWM2_CLK_EN_R {
+        PWM2_CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - Set 1 to enable PWM3 clock"]
+    #[inline(always)]
+    pub fn pwm3_clk_en(&self) -> PWM3_CLK_EN_R {
+        PWM3_CLK_EN_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - Set 1 to enable SPI4 clock"]
+    #[inline(always)]
+    pub fn spi3_dma_clk_en(&self) -> SPI3_DMA_CLK_EN_R {
+        SPI3_DMA_CLK_EN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - Set 1 to enable APB_SARADC clock"]
+    #[inline(always)]
+    pub fn apb_saradc_clk_en(&self) -> APB_SARADC_CLK_EN_R {
+        APB_SARADC_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - Set 1 to enable SYSTEMTIMER clock"]
+    #[inline(always)]
+    pub fn systimer_clk_en(&self) -> SYSTIMER_CLK_EN_R {
+        SYSTIMER_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - Set 1 to enable ADC2_ARB clock"]
+    #[inline(always)]
+    pub fn adc2_arb_clk_en(&self) -> ADC2_ARB_CLK_EN_R {
+        ADC2_ARB_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Set 1 to enable SPI4 clock"]
+    #[inline(always)]
+    pub fn spi4_clk_en(&self) -> SPI4_CLK_EN_R {
+        SPI4_CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PERIP_CLK_EN0")
+            .field("timers_clk_en", &self.timers_clk_en())
+            .field("spi01_clk_en", &self.spi01_clk_en())
+            .field("uart_clk_en", &self.uart_clk_en())
+            .field("wdg_clk_en", &self.wdg_clk_en())
+            .field("i2s0_clk_en", &self.i2s0_clk_en())
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
+            .field("uhci0_clk_en", &self.uhci0_clk_en())
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("uhci1_clk_en", &self.uhci1_clk_en())
+            .field("timergroup_clk_en", &self.timergroup_clk_en())
+            .field("efuse_clk_en", &self.efuse_clk_en())
+            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
+            .field("spi3_clk_en", &self.spi3_clk_en())
+            .field("pwm0_clk_en", &self.pwm0_clk_en())
+            .field("i2c_ext1_clk_en", &self.i2c_ext1_clk_en())
+            .field("twai_clk_en", &self.twai_clk_en())
+            .field("pwm1_clk_en", &self.pwm1_clk_en())
+            .field("i2s1_clk_en", &self.i2s1_clk_en())
+            .field("spi2_dma_clk_en", &self.spi2_dma_clk_en())
+            .field("usb_clk_en", &self.usb_clk_en())
+            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
+            .field("pwm2_clk_en", &self.pwm2_clk_en())
+            .field("pwm3_clk_en", &self.pwm3_clk_en())
+            .field("spi3_dma_clk_en", &self.spi3_dma_clk_en())
+            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
+            .field("spi4_clk_en", &self.spi4_clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to enable TIMERS clock"]
+    #[inline(always)]
+    pub fn timers_clk_en(&mut self) -> TIMERS_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        TIMERS_CLK_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to enable SPI01 clock"]
+    #[inline(always)]
+    pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SPI01_CLK_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to enable UART clock"]
+    #[inline(always)]
+    pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        UART_CLK_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to enable WDG clock"]
+    #[inline(always)]
+    pub fn wdg_clk_en(&mut self) -> WDG_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        WDG_CLK_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set 1 to enable I2S0 clock"]
+    #[inline(always)]
+    pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        I2S0_CLK_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set 1 to enable UART1 clock"]
+    #[inline(always)]
+    pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        UART1_CLK_EN_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set 1 to enable SPI2 clock"]
+    #[inline(always)]
+    pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SPI2_CLK_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set 1 to enable I2C_EXT0 clock"]
+    #[inline(always)]
+    pub fn i2c_ext0_clk_en(&mut self) -> I2C_EXT0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        I2C_EXT0_CLK_EN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set 1 to enable UHCI0 clock"]
+    #[inline(always)]
+    pub fn uhci0_clk_en(&mut self) -> UHCI0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        UHCI0_CLK_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set 1 to enable RMT clock"]
+    #[inline(always)]
+    pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        RMT_CLK_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Set 1 to enable PCNT clock"]
+    #[inline(always)]
+    pub fn pcnt_clk_en(&mut self) -> PCNT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        PCNT_CLK_EN_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Set 1 to enable LEDC clock"]
+    #[inline(always)]
+    pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        LEDC_CLK_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - Set 1 to enable UHCI1 clock"]
+    #[inline(always)]
+    pub fn uhci1_clk_en(&mut self) -> UHCI1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        UHCI1_CLK_EN_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - Set 1 to enable TIMERGROUP clock"]
+    #[inline(always)]
+    pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        TIMERGROUP_CLK_EN_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - Set 1 to enable EFUSE clock"]
+    #[inline(always)]
+    pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        EFUSE_CLK_EN_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - Set 1 to enable TIMERGROUP1 clock"]
+    #[inline(always)]
+    pub fn timergroup1_clk_en(&mut self) -> TIMERGROUP1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        TIMERGROUP1_CLK_EN_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - Set 1 to enable SPI3 clock"]
+    #[inline(always)]
+    pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SPI3_CLK_EN_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Set 1 to enable PWM0 clock"]
+    #[inline(always)]
+    pub fn pwm0_clk_en(&mut self) -> PWM0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        PWM0_CLK_EN_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - Set 1 to enable I2C_EXT1 clock"]
+    #[inline(always)]
+    pub fn i2c_ext1_clk_en(&mut self) -> I2C_EXT1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        I2C_EXT1_CLK_EN_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - Set 1 to enable CAN clock"]
+    #[inline(always)]
+    pub fn twai_clk_en(&mut self) -> TWAI_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        TWAI_CLK_EN_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - Set 1 to enable PWM1 clock"]
+    #[inline(always)]
+    pub fn pwm1_clk_en(&mut self) -> PWM1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        PWM1_CLK_EN_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - Set 1 to enable I2S1 clock"]
+    #[inline(always)]
+    pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        I2S1_CLK_EN_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Set 1 to enable SPI2_DMA clock"]
+    #[inline(always)]
+    pub fn spi2_dma_clk_en(&mut self) -> SPI2_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SPI2_DMA_CLK_EN_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - Set 1 to enable USB clock"]
+    #[inline(always)]
+    pub fn usb_clk_en(&mut self) -> USB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        USB_CLK_EN_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - Set 1 to enable UART_MEM clock"]
+    #[inline(always)]
+    pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        UART_MEM_CLK_EN_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - Set 1 to enable PWM2 clock"]
+    #[inline(always)]
+    pub fn pwm2_clk_en(&mut self) -> PWM2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        PWM2_CLK_EN_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - Set 1 to enable PWM3 clock"]
+    #[inline(always)]
+    pub fn pwm3_clk_en(&mut self) -> PWM3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        PWM3_CLK_EN_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - Set 1 to enable SPI4 clock"]
+    #[inline(always)]
+    pub fn spi3_dma_clk_en(&mut self) -> SPI3_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SPI3_DMA_CLK_EN_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - Set 1 to enable APB_SARADC clock"]
+    #[inline(always)]
+    pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        APB_SARADC_CLK_EN_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - Set 1 to enable SYSTEMTIMER clock"]
+    #[inline(always)]
+    pub fn systimer_clk_en(&mut self) -> SYSTIMER_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SYSTIMER_CLK_EN_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - Set 1 to enable ADC2_ARB clock"]
+    #[inline(always)]
+    pub fn adc2_arb_clk_en(&mut self) -> ADC2_ARB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        ADC2_ARB_CLK_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - Set 1 to enable SPI4 clock"]
+    #[inline(always)]
+    pub fn spi4_clk_en(&mut self) -> SPI4_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
+        SPI4_CLK_EN_W::new(self, 31)
+    }
+}
+#[doc = "peripheral clock configuration regsiter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PERIP_CLK_EN0_SPEC;
+impl crate::RegisterSpec for PERIP_CLK_EN0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perip_clk_en0::R`](R) reader structure"]
+impl crate::Readable for PERIP_CLK_EN0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`perip_clk_en0::W`](W) writer structure"]
+impl crate::Writable for PERIP_CLK_EN0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIP_CLK_EN0 to value 0xf9c1_e06f"]
+impl crate::Resettable for PERIP_CLK_EN0_SPEC {
+    const RESET_VALUE: u32 = 0xf9c1_e06f;
+}

vendor/esp32s3/src/system/perip_clk_en1.rs

@@ -0,0 +1,197 @@
+#[doc = "Register `PERIP_CLK_EN1` reader"]
+pub type R = crate::R<PERIP_CLK_EN1_SPEC>;
+#[doc = "Register `PERIP_CLK_EN1` writer"]
+pub type W = crate::W<PERIP_CLK_EN1_SPEC>;
+#[doc = "Field `PERI_BACKUP_CLK_EN` reader - Set 1 to enable BACKUP clock"]
+pub type PERI_BACKUP_CLK_EN_R = crate::BitReader;
+#[doc = "Field `PERI_BACKUP_CLK_EN` writer - Set 1 to enable BACKUP clock"]
+pub type PERI_BACKUP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_AES_CLK_EN` reader - Set 1 to enable AES clock"]
+pub type CRYPTO_AES_CLK_EN_R = crate::BitReader;
+#[doc = "Field `CRYPTO_AES_CLK_EN` writer - Set 1 to enable AES clock"]
+pub type CRYPTO_AES_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_SHA_CLK_EN` reader - Set 1 to enable SHA clock"]
+pub type CRYPTO_SHA_CLK_EN_R = crate::BitReader;
+#[doc = "Field `CRYPTO_SHA_CLK_EN` writer - Set 1 to enable SHA clock"]
+pub type CRYPTO_SHA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_RSA_CLK_EN` reader - Set 1 to enable RSA clock"]
+pub type CRYPTO_RSA_CLK_EN_R = crate::BitReader;
+#[doc = "Field `CRYPTO_RSA_CLK_EN` writer - Set 1 to enable RSA clock"]
+pub type CRYPTO_RSA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_DS_CLK_EN` reader - Set 1 to enable DS clock"]
+pub type CRYPTO_DS_CLK_EN_R = crate::BitReader;
+#[doc = "Field `CRYPTO_DS_CLK_EN` writer - Set 1 to enable DS clock"]
+pub type CRYPTO_DS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_HMAC_CLK_EN` reader - Set 1 to enable HMAC clock"]
+pub type CRYPTO_HMAC_CLK_EN_R = crate::BitReader;
+#[doc = "Field `CRYPTO_HMAC_CLK_EN` writer - Set 1 to enable HMAC clock"]
+pub type CRYPTO_HMAC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DMA_CLK_EN` reader - Set 1 to enable DMA clock"]
+pub type DMA_CLK_EN_R = crate::BitReader;
+#[doc = "Field `DMA_CLK_EN` writer - Set 1 to enable DMA clock"]
+pub type DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_HOST_CLK_EN` reader - Set 1 to enable SDIO_HOST clock"]
+pub type SDIO_HOST_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SDIO_HOST_CLK_EN` writer - Set 1 to enable SDIO_HOST clock"]
+pub type SDIO_HOST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LCD_CAM_CLK_EN` reader - Set 1 to enable LCD_CAM clock"]
+pub type LCD_CAM_CLK_EN_R = crate::BitReader;
+#[doc = "Field `LCD_CAM_CLK_EN` writer - Set 1 to enable LCD_CAM clock"]
+pub type LCD_CAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART2_CLK_EN` reader - Set 1 to enable UART2 clock"]
+pub type UART2_CLK_EN_R = crate::BitReader;
+#[doc = "Field `UART2_CLK_EN` writer - Set 1 to enable UART2 clock"]
+pub type UART2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_DEVICE_CLK_EN` reader - Set 1 to enable USB_DEVICE clock"]
+pub type USB_DEVICE_CLK_EN_R = crate::BitReader;
+#[doc = "Field `USB_DEVICE_CLK_EN` writer - Set 1 to enable USB_DEVICE clock"]
+pub type USB_DEVICE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to enable BACKUP clock"]
+    #[inline(always)]
+    pub fn peri_backup_clk_en(&self) -> PERI_BACKUP_CLK_EN_R {
+        PERI_BACKUP_CLK_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to enable AES clock"]
+    #[inline(always)]
+    pub fn crypto_aes_clk_en(&self) -> CRYPTO_AES_CLK_EN_R {
+        CRYPTO_AES_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to enable SHA clock"]
+    #[inline(always)]
+    pub fn crypto_sha_clk_en(&self) -> CRYPTO_SHA_CLK_EN_R {
+        CRYPTO_SHA_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to enable RSA clock"]
+    #[inline(always)]
+    pub fn crypto_rsa_clk_en(&self) -> CRYPTO_RSA_CLK_EN_R {
+        CRYPTO_RSA_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set 1 to enable DS clock"]
+    #[inline(always)]
+    pub fn crypto_ds_clk_en(&self) -> CRYPTO_DS_CLK_EN_R {
+        CRYPTO_DS_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set 1 to enable HMAC clock"]
+    #[inline(always)]
+    pub fn crypto_hmac_clk_en(&self) -> CRYPTO_HMAC_CLK_EN_R {
+        CRYPTO_HMAC_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set 1 to enable DMA clock"]
+    #[inline(always)]
+    pub fn dma_clk_en(&self) -> DMA_CLK_EN_R {
+        DMA_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set 1 to enable SDIO_HOST clock"]
+    #[inline(always)]
+    pub fn sdio_host_clk_en(&self) -> SDIO_HOST_CLK_EN_R {
+        SDIO_HOST_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set 1 to enable LCD_CAM clock"]
+    #[inline(always)]
+    pub fn lcd_cam_clk_en(&self) -> LCD_CAM_CLK_EN_R {
+        LCD_CAM_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Set 1 to enable UART2 clock"]
+    #[inline(always)]
+    pub fn uart2_clk_en(&self) -> UART2_CLK_EN_R {
+        UART2_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Set 1 to enable USB_DEVICE clock"]
+    #[inline(always)]
+    pub fn usb_device_clk_en(&self) -> USB_DEVICE_CLK_EN_R {
+        USB_DEVICE_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PERIP_CLK_EN1")
+            .field("peri_backup_clk_en", &self.peri_backup_clk_en())
+            .field("crypto_aes_clk_en", &self.crypto_aes_clk_en())
+            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
+            .field("crypto_rsa_clk_en", &self.crypto_rsa_clk_en())
+            .field("crypto_ds_clk_en", &self.crypto_ds_clk_en())
+            .field("crypto_hmac_clk_en", &self.crypto_hmac_clk_en())
+            .field("dma_clk_en", &self.dma_clk_en())
+            .field("sdio_host_clk_en", &self.sdio_host_clk_en())
+            .field("lcd_cam_clk_en", &self.lcd_cam_clk_en())
+            .field("uart2_clk_en", &self.uart2_clk_en())
+            .field("usb_device_clk_en", &self.usb_device_clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to enable BACKUP clock"]
+    #[inline(always)]
+    pub fn peri_backup_clk_en(&mut self) -> PERI_BACKUP_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        PERI_BACKUP_CLK_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to enable AES clock"]
+    #[inline(always)]
+    pub fn crypto_aes_clk_en(&mut self) -> CRYPTO_AES_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        CRYPTO_AES_CLK_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to enable SHA clock"]
+    #[inline(always)]
+    pub fn crypto_sha_clk_en(&mut self) -> CRYPTO_SHA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        CRYPTO_SHA_CLK_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to enable RSA clock"]
+    #[inline(always)]
+    pub fn crypto_rsa_clk_en(&mut self) -> CRYPTO_RSA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        CRYPTO_RSA_CLK_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set 1 to enable DS clock"]
+    #[inline(always)]
+    pub fn crypto_ds_clk_en(&mut self) -> CRYPTO_DS_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        CRYPTO_DS_CLK_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set 1 to enable HMAC clock"]
+    #[inline(always)]
+    pub fn crypto_hmac_clk_en(&mut self) -> CRYPTO_HMAC_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        CRYPTO_HMAC_CLK_EN_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set 1 to enable DMA clock"]
+    #[inline(always)]
+    pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        DMA_CLK_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set 1 to enable SDIO_HOST clock"]
+    #[inline(always)]
+    pub fn sdio_host_clk_en(&mut self) -> SDIO_HOST_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        SDIO_HOST_CLK_EN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set 1 to enable LCD_CAM clock"]
+    #[inline(always)]
+    pub fn lcd_cam_clk_en(&mut self) -> LCD_CAM_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        LCD_CAM_CLK_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set 1 to enable UART2 clock"]
+    #[inline(always)]
+    pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        UART2_CLK_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Set 1 to enable USB_DEVICE clock"]
+    #[inline(always)]
+    pub fn usb_device_clk_en(&mut self) -> USB_DEVICE_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
+        USB_DEVICE_CLK_EN_W::new(self, 10)
+    }
+}
+#[doc = "peripheral clock configuration regsiter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PERIP_CLK_EN1_SPEC;
+impl crate::RegisterSpec for PERIP_CLK_EN1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perip_clk_en1::R`](R) reader structure"]
+impl crate::Readable for PERIP_CLK_EN1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`perip_clk_en1::W`](W) writer structure"]
+impl crate::Writable for PERIP_CLK_EN1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIP_CLK_EN1 to value 0x0600"]
+impl crate::Resettable for PERIP_CLK_EN1_SPEC {
+    const RESET_VALUE: u32 = 0x0600;
+}

vendor/esp32s3/src/system/perip_rst_en0.rs

@@ -0,0 +1,512 @@
+#[doc = "Register `PERIP_RST_EN0` reader"]
+pub type R = crate::R<PERIP_RST_EN0_SPEC>;
+#[doc = "Register `PERIP_RST_EN0` writer"]
+pub type W = crate::W<PERIP_RST_EN0_SPEC>;
+#[doc = "Field `TIMERS_RST` reader - Set 1 to let TIMERS reset"]
+pub type TIMERS_RST_R = crate::BitReader;
+#[doc = "Field `TIMERS_RST` writer - Set 1 to let TIMERS reset"]
+pub type TIMERS_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI01_RST` reader - Set 1 to let SPI01 reset"]
+pub type SPI01_RST_R = crate::BitReader;
+#[doc = "Field `SPI01_RST` writer - Set 1 to let SPI01 reset"]
+pub type SPI01_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_RST` reader - Set 1 to let UART reset"]
+pub type UART_RST_R = crate::BitReader;
+#[doc = "Field `UART_RST` writer - Set 1 to let UART reset"]
+pub type UART_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDG_RST` reader - Set 1 to let WDG reset"]
+pub type WDG_RST_R = crate::BitReader;
+#[doc = "Field `WDG_RST` writer - Set 1 to let WDG reset"]
+pub type WDG_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2S0_RST` reader - Set 1 to let I2S0 reset"]
+pub type I2S0_RST_R = crate::BitReader;
+#[doc = "Field `I2S0_RST` writer - Set 1 to let I2S0 reset"]
+pub type I2S0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART1_RST` reader - Set 1 to let UART1 reset"]
+pub type UART1_RST_R = crate::BitReader;
+#[doc = "Field `UART1_RST` writer - Set 1 to let UART1 reset"]
+pub type UART1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI2_RST` reader - Set 1 to let SPI2 reset"]
+pub type SPI2_RST_R = crate::BitReader;
+#[doc = "Field `SPI2_RST` writer - Set 1 to let SPI2 reset"]
+pub type SPI2_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_EXT0_RST` reader - Set 1 to let I2C_EXT0 reset"]
+pub type I2C_EXT0_RST_R = crate::BitReader;
+#[doc = "Field `I2C_EXT0_RST` writer - Set 1 to let I2C_EXT0 reset"]
+pub type I2C_EXT0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UHCI0_RST` reader - Set 1 to let UHCI0 reset"]
+pub type UHCI0_RST_R = crate::BitReader;
+#[doc = "Field `UHCI0_RST` writer - Set 1 to let UHCI0 reset"]
+pub type UHCI0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RMT_RST` reader - Set 1 to let RMT reset"]
+pub type RMT_RST_R = crate::BitReader;
+#[doc = "Field `RMT_RST` writer - Set 1 to let RMT reset"]
+pub type RMT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PCNT_RST` reader - Set 1 to let PCNT reset"]
+pub type PCNT_RST_R = crate::BitReader;
+#[doc = "Field `PCNT_RST` writer - Set 1 to let PCNT reset"]
+pub type PCNT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LEDC_RST` reader - Set 1 to let LEDC reset"]
+pub type LEDC_RST_R = crate::BitReader;
+#[doc = "Field `LEDC_RST` writer - Set 1 to let LEDC reset"]
+pub type LEDC_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UHCI1_RST` reader - Set 1 to let UHCI1 reset"]
+pub type UHCI1_RST_R = crate::BitReader;
+#[doc = "Field `UHCI1_RST` writer - Set 1 to let UHCI1 reset"]
+pub type UHCI1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMERGROUP_RST` reader - Set 1 to let TIMERGROUP reset"]
+pub type TIMERGROUP_RST_R = crate::BitReader;
+#[doc = "Field `TIMERGROUP_RST` writer - Set 1 to let TIMERGROUP reset"]
+pub type TIMERGROUP_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EFUSE_RST` reader - Set 1 to let EFUSE reset"]
+pub type EFUSE_RST_R = crate::BitReader;
+#[doc = "Field `EFUSE_RST` writer - Set 1 to let EFUSE reset"]
+pub type EFUSE_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMERGROUP1_RST` reader - Set 1 to let TIMERGROUP1 reset"]
+pub type TIMERGROUP1_RST_R = crate::BitReader;
+#[doc = "Field `TIMERGROUP1_RST` writer - Set 1 to let TIMERGROUP1 reset"]
+pub type TIMERGROUP1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI3_RST` reader - Set 1 to let SPI3 reset"]
+pub type SPI3_RST_R = crate::BitReader;
+#[doc = "Field `SPI3_RST` writer - Set 1 to let SPI3 reset"]
+pub type SPI3_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM0_RST` reader - Set 1 to let PWM0 reset"]
+pub type PWM0_RST_R = crate::BitReader;
+#[doc = "Field `PWM0_RST` writer - Set 1 to let PWM0 reset"]
+pub type PWM0_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_EXT1_RST` reader - Set 1 to let I2C_EXT1 reset"]
+pub type I2C_EXT1_RST_R = crate::BitReader;
+#[doc = "Field `I2C_EXT1_RST` writer - Set 1 to let I2C_EXT1 reset"]
+pub type I2C_EXT1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TWAI_RST` reader - Set 1 to let CAN reset"]
+pub type TWAI_RST_R = crate::BitReader;
+#[doc = "Field `TWAI_RST` writer - Set 1 to let CAN reset"]
+pub type TWAI_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM1_RST` reader - Set 1 to let PWM1 reset"]
+pub type PWM1_RST_R = crate::BitReader;
+#[doc = "Field `PWM1_RST` writer - Set 1 to let PWM1 reset"]
+pub type PWM1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2S1_RST` reader - Set 1 to let I2S1 reset"]
+pub type I2S1_RST_R = crate::BitReader;
+#[doc = "Field `I2S1_RST` writer - Set 1 to let I2S1 reset"]
+pub type I2S1_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI2_DMA_RST` reader - Set 1 to let SPI2 reset"]
+pub type SPI2_DMA_RST_R = crate::BitReader;
+#[doc = "Field `SPI2_DMA_RST` writer - Set 1 to let SPI2 reset"]
+pub type SPI2_DMA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_RST` reader - Set 1 to let USB reset"]
+pub type USB_RST_R = crate::BitReader;
+#[doc = "Field `USB_RST` writer - Set 1 to let USB reset"]
+pub type USB_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_MEM_RST` reader - Set 1 to let UART_MEM reset"]
+pub type UART_MEM_RST_R = crate::BitReader;
+#[doc = "Field `UART_MEM_RST` writer - Set 1 to let UART_MEM reset"]
+pub type UART_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM2_RST` reader - Set 1 to let PWM2 reset"]
+pub type PWM2_RST_R = crate::BitReader;
+#[doc = "Field `PWM2_RST` writer - Set 1 to let PWM2 reset"]
+pub type PWM2_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PWM3_RST` reader - Set 1 to let PWM3 reset"]
+pub type PWM3_RST_R = crate::BitReader;
+#[doc = "Field `PWM3_RST` writer - Set 1 to let PWM3 reset"]
+pub type PWM3_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI3_DMA_RST` reader - Set 1 to let SPI3 reset"]
+pub type SPI3_DMA_RST_R = crate::BitReader;
+#[doc = "Field `SPI3_DMA_RST` writer - Set 1 to let SPI3 reset"]
+pub type SPI3_DMA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APB_SARADC_RST` reader - Set 1 to let APB_SARADC reset"]
+pub type APB_SARADC_RST_R = crate::BitReader;
+#[doc = "Field `APB_SARADC_RST` writer - Set 1 to let APB_SARADC reset"]
+pub type APB_SARADC_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SYSTIMER_RST` reader - Set 1 to let SYSTIMER reset"]
+pub type SYSTIMER_RST_R = crate::BitReader;
+#[doc = "Field `SYSTIMER_RST` writer - Set 1 to let SYSTIMER reset"]
+pub type SYSTIMER_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC2_ARB_RST` reader - Set 1 to let ADC2_ARB reset"]
+pub type ADC2_ARB_RST_R = crate::BitReader;
+#[doc = "Field `ADC2_ARB_RST` writer - Set 1 to let ADC2_ARB reset"]
+pub type ADC2_ARB_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI4_RST` reader - Set 1 to let SPI4 reset"]
+pub type SPI4_RST_R = crate::BitReader;
+#[doc = "Field `SPI4_RST` writer - Set 1 to let SPI4 reset"]
+pub type SPI4_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to let TIMERS reset"]
+    #[inline(always)]
+    pub fn timers_rst(&self) -> TIMERS_RST_R {
+        TIMERS_RST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let SPI01 reset"]
+    #[inline(always)]
+    pub fn spi01_rst(&self) -> SPI01_RST_R {
+        SPI01_RST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to let UART reset"]
+    #[inline(always)]
+    pub fn uart_rst(&self) -> UART_RST_R {
+        UART_RST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to let WDG reset"]
+    #[inline(always)]
+    pub fn wdg_rst(&self) -> WDG_RST_R {
+        WDG_RST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set 1 to let I2S0 reset"]
+    #[inline(always)]
+    pub fn i2s0_rst(&self) -> I2S0_RST_R {
+        I2S0_RST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set 1 to let UART1 reset"]
+    #[inline(always)]
+    pub fn uart1_rst(&self) -> UART1_RST_R {
+        UART1_RST_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set 1 to let SPI2 reset"]
+    #[inline(always)]
+    pub fn spi2_rst(&self) -> SPI2_RST_R {
+        SPI2_RST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set 1 to let I2C_EXT0 reset"]
+    #[inline(always)]
+    pub fn i2c_ext0_rst(&self) -> I2C_EXT0_RST_R {
+        I2C_EXT0_RST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set 1 to let UHCI0 reset"]
+    #[inline(always)]
+    pub fn uhci0_rst(&self) -> UHCI0_RST_R {
+        UHCI0_RST_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Set 1 to let RMT reset"]
+    #[inline(always)]
+    pub fn rmt_rst(&self) -> RMT_RST_R {
+        RMT_RST_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Set 1 to let PCNT reset"]
+    #[inline(always)]
+    pub fn pcnt_rst(&self) -> PCNT_RST_R {
+        PCNT_RST_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Set 1 to let LEDC reset"]
+    #[inline(always)]
+    pub fn ledc_rst(&self) -> LEDC_RST_R {
+        LEDC_RST_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Set 1 to let UHCI1 reset"]
+    #[inline(always)]
+    pub fn uhci1_rst(&self) -> UHCI1_RST_R {
+        UHCI1_RST_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Set 1 to let TIMERGROUP reset"]
+    #[inline(always)]
+    pub fn timergroup_rst(&self) -> TIMERGROUP_RST_R {
+        TIMERGROUP_RST_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - Set 1 to let EFUSE reset"]
+    #[inline(always)]
+    pub fn efuse_rst(&self) -> EFUSE_RST_R {
+        EFUSE_RST_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Set 1 to let TIMERGROUP1 reset"]
+    #[inline(always)]
+    pub fn timergroup1_rst(&self) -> TIMERGROUP1_RST_R {
+        TIMERGROUP1_RST_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Set 1 to let SPI3 reset"]
+    #[inline(always)]
+    pub fn spi3_rst(&self) -> SPI3_RST_R {
+        SPI3_RST_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Set 1 to let PWM0 reset"]
+    #[inline(always)]
+    pub fn pwm0_rst(&self) -> PWM0_RST_R {
+        PWM0_RST_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Set 1 to let I2C_EXT1 reset"]
+    #[inline(always)]
+    pub fn i2c_ext1_rst(&self) -> I2C_EXT1_RST_R {
+        I2C_EXT1_RST_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Set 1 to let CAN reset"]
+    #[inline(always)]
+    pub fn twai_rst(&self) -> TWAI_RST_R {
+        TWAI_RST_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - Set 1 to let PWM1 reset"]
+    #[inline(always)]
+    pub fn pwm1_rst(&self) -> PWM1_RST_R {
+        PWM1_RST_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Set 1 to let I2S1 reset"]
+    #[inline(always)]
+    pub fn i2s1_rst(&self) -> I2S1_RST_R {
+        I2S1_RST_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Set 1 to let SPI2 reset"]
+    #[inline(always)]
+    pub fn spi2_dma_rst(&self) -> SPI2_DMA_RST_R {
+        SPI2_DMA_RST_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Set 1 to let USB reset"]
+    #[inline(always)]
+    pub fn usb_rst(&self) -> USB_RST_R {
+        USB_RST_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Set 1 to let UART_MEM reset"]
+    #[inline(always)]
+    pub fn uart_mem_rst(&self) -> UART_MEM_RST_R {
+        UART_MEM_RST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - Set 1 to let PWM2 reset"]
+    #[inline(always)]
+    pub fn pwm2_rst(&self) -> PWM2_RST_R {
+        PWM2_RST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - Set 1 to let PWM3 reset"]
+    #[inline(always)]
+    pub fn pwm3_rst(&self) -> PWM3_RST_R {
+        PWM3_RST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - Set 1 to let SPI3 reset"]
+    #[inline(always)]
+    pub fn spi3_dma_rst(&self) -> SPI3_DMA_RST_R {
+        SPI3_DMA_RST_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - Set 1 to let APB_SARADC reset"]
+    #[inline(always)]
+    pub fn apb_saradc_rst(&self) -> APB_SARADC_RST_R {
+        APB_SARADC_RST_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - Set 1 to let SYSTIMER reset"]
+    #[inline(always)]
+    pub fn systimer_rst(&self) -> SYSTIMER_RST_R {
+        SYSTIMER_RST_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - Set 1 to let ADC2_ARB reset"]
+    #[inline(always)]
+    pub fn adc2_arb_rst(&self) -> ADC2_ARB_RST_R {
+        ADC2_ARB_RST_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Set 1 to let SPI4 reset"]
+    #[inline(always)]
+    pub fn spi4_rst(&self) -> SPI4_RST_R {
+        SPI4_RST_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PERIP_RST_EN0")
+            .field("timers_rst", &self.timers_rst())
+            .field("spi01_rst", &self.spi01_rst())
+            .field("uart_rst", &self.uart_rst())
+            .field("wdg_rst", &self.wdg_rst())
+            .field("i2s0_rst", &self.i2s0_rst())
+            .field("uart1_rst", &self.uart1_rst())
+            .field("spi2_rst", &self.spi2_rst())
+            .field("i2c_ext0_rst", &self.i2c_ext0_rst())
+            .field("uhci0_rst", &self.uhci0_rst())
+            .field("rmt_rst", &self.rmt_rst())
+            .field("pcnt_rst", &self.pcnt_rst())
+            .field("ledc_rst", &self.ledc_rst())
+            .field("uhci1_rst", &self.uhci1_rst())
+            .field("timergroup_rst", &self.timergroup_rst())
+            .field("efuse_rst", &self.efuse_rst())
+            .field("timergroup1_rst", &self.timergroup1_rst())
+            .field("spi3_rst", &self.spi3_rst())
+            .field("pwm0_rst", &self.pwm0_rst())
+            .field("i2c_ext1_rst", &self.i2c_ext1_rst())
+            .field("twai_rst", &self.twai_rst())
+            .field("pwm1_rst", &self.pwm1_rst())
+            .field("i2s1_rst", &self.i2s1_rst())
+            .field("spi2_dma_rst", &self.spi2_dma_rst())
+            .field("usb_rst", &self.usb_rst())
+            .field("uart_mem_rst", &self.uart_mem_rst())
+            .field("pwm2_rst", &self.pwm2_rst())
+            .field("pwm3_rst", &self.pwm3_rst())
+            .field("spi3_dma_rst", &self.spi3_dma_rst())
+            .field("apb_saradc_rst", &self.apb_saradc_rst())
+            .field("systimer_rst", &self.systimer_rst())
+            .field("adc2_arb_rst", &self.adc2_arb_rst())
+            .field("spi4_rst", &self.spi4_rst())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to let TIMERS reset"]
+    #[inline(always)]
+    pub fn timers_rst(&mut self) -> TIMERS_RST_W<PERIP_RST_EN0_SPEC> {
+        TIMERS_RST_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let SPI01 reset"]
+    #[inline(always)]
+    pub fn spi01_rst(&mut self) -> SPI01_RST_W<PERIP_RST_EN0_SPEC> {
+        SPI01_RST_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to let UART reset"]
+    #[inline(always)]
+    pub fn uart_rst(&mut self) -> UART_RST_W<PERIP_RST_EN0_SPEC> {
+        UART_RST_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to let WDG reset"]
+    #[inline(always)]
+    pub fn wdg_rst(&mut self) -> WDG_RST_W<PERIP_RST_EN0_SPEC> {
+        WDG_RST_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set 1 to let I2S0 reset"]
+    #[inline(always)]
+    pub fn i2s0_rst(&mut self) -> I2S0_RST_W<PERIP_RST_EN0_SPEC> {
+        I2S0_RST_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set 1 to let UART1 reset"]
+    #[inline(always)]
+    pub fn uart1_rst(&mut self) -> UART1_RST_W<PERIP_RST_EN0_SPEC> {
+        UART1_RST_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set 1 to let SPI2 reset"]
+    #[inline(always)]
+    pub fn spi2_rst(&mut self) -> SPI2_RST_W<PERIP_RST_EN0_SPEC> {
+        SPI2_RST_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set 1 to let I2C_EXT0 reset"]
+    #[inline(always)]
+    pub fn i2c_ext0_rst(&mut self) -> I2C_EXT0_RST_W<PERIP_RST_EN0_SPEC> {
+        I2C_EXT0_RST_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set 1 to let UHCI0 reset"]
+    #[inline(always)]
+    pub fn uhci0_rst(&mut self) -> UHCI0_RST_W<PERIP_RST_EN0_SPEC> {
+        UHCI0_RST_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set 1 to let RMT reset"]
+    #[inline(always)]
+    pub fn rmt_rst(&mut self) -> RMT_RST_W<PERIP_RST_EN0_SPEC> {
+        RMT_RST_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Set 1 to let PCNT reset"]
+    #[inline(always)]
+    pub fn pcnt_rst(&mut self) -> PCNT_RST_W<PERIP_RST_EN0_SPEC> {
+        PCNT_RST_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Set 1 to let LEDC reset"]
+    #[inline(always)]
+    pub fn ledc_rst(&mut self) -> LEDC_RST_W<PERIP_RST_EN0_SPEC> {
+        LEDC_RST_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - Set 1 to let UHCI1 reset"]
+    #[inline(always)]
+    pub fn uhci1_rst(&mut self) -> UHCI1_RST_W<PERIP_RST_EN0_SPEC> {
+        UHCI1_RST_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - Set 1 to let TIMERGROUP reset"]
+    #[inline(always)]
+    pub fn timergroup_rst(&mut self) -> TIMERGROUP_RST_W<PERIP_RST_EN0_SPEC> {
+        TIMERGROUP_RST_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - Set 1 to let EFUSE reset"]
+    #[inline(always)]
+    pub fn efuse_rst(&mut self) -> EFUSE_RST_W<PERIP_RST_EN0_SPEC> {
+        EFUSE_RST_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - Set 1 to let TIMERGROUP1 reset"]
+    #[inline(always)]
+    pub fn timergroup1_rst(&mut self) -> TIMERGROUP1_RST_W<PERIP_RST_EN0_SPEC> {
+        TIMERGROUP1_RST_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - Set 1 to let SPI3 reset"]
+    #[inline(always)]
+    pub fn spi3_rst(&mut self) -> SPI3_RST_W<PERIP_RST_EN0_SPEC> {
+        SPI3_RST_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Set 1 to let PWM0 reset"]
+    #[inline(always)]
+    pub fn pwm0_rst(&mut self) -> PWM0_RST_W<PERIP_RST_EN0_SPEC> {
+        PWM0_RST_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - Set 1 to let I2C_EXT1 reset"]
+    #[inline(always)]
+    pub fn i2c_ext1_rst(&mut self) -> I2C_EXT1_RST_W<PERIP_RST_EN0_SPEC> {
+        I2C_EXT1_RST_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - Set 1 to let CAN reset"]
+    #[inline(always)]
+    pub fn twai_rst(&mut self) -> TWAI_RST_W<PERIP_RST_EN0_SPEC> {
+        TWAI_RST_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - Set 1 to let PWM1 reset"]
+    #[inline(always)]
+    pub fn pwm1_rst(&mut self) -> PWM1_RST_W<PERIP_RST_EN0_SPEC> {
+        PWM1_RST_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - Set 1 to let I2S1 reset"]
+    #[inline(always)]
+    pub fn i2s1_rst(&mut self) -> I2S1_RST_W<PERIP_RST_EN0_SPEC> {
+        I2S1_RST_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Set 1 to let SPI2 reset"]
+    #[inline(always)]
+    pub fn spi2_dma_rst(&mut self) -> SPI2_DMA_RST_W<PERIP_RST_EN0_SPEC> {
+        SPI2_DMA_RST_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - Set 1 to let USB reset"]
+    #[inline(always)]
+    pub fn usb_rst(&mut self) -> USB_RST_W<PERIP_RST_EN0_SPEC> {
+        USB_RST_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - Set 1 to let UART_MEM reset"]
+    #[inline(always)]
+    pub fn uart_mem_rst(&mut self) -> UART_MEM_RST_W<PERIP_RST_EN0_SPEC> {
+        UART_MEM_RST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - Set 1 to let PWM2 reset"]
+    #[inline(always)]
+    pub fn pwm2_rst(&mut self) -> PWM2_RST_W<PERIP_RST_EN0_SPEC> {
+        PWM2_RST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - Set 1 to let PWM3 reset"]
+    #[inline(always)]
+    pub fn pwm3_rst(&mut self) -> PWM3_RST_W<PERIP_RST_EN0_SPEC> {
+        PWM3_RST_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - Set 1 to let SPI3 reset"]
+    #[inline(always)]
+    pub fn spi3_dma_rst(&mut self) -> SPI3_DMA_RST_W<PERIP_RST_EN0_SPEC> {
+        SPI3_DMA_RST_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - Set 1 to let APB_SARADC reset"]
+    #[inline(always)]
+    pub fn apb_saradc_rst(&mut self) -> APB_SARADC_RST_W<PERIP_RST_EN0_SPEC> {
+        APB_SARADC_RST_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - Set 1 to let SYSTIMER reset"]
+    #[inline(always)]
+    pub fn systimer_rst(&mut self) -> SYSTIMER_RST_W<PERIP_RST_EN0_SPEC> {
+        SYSTIMER_RST_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - Set 1 to let ADC2_ARB reset"]
+    #[inline(always)]
+    pub fn adc2_arb_rst(&mut self) -> ADC2_ARB_RST_W<PERIP_RST_EN0_SPEC> {
+        ADC2_ARB_RST_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - Set 1 to let SPI4 reset"]
+    #[inline(always)]
+    pub fn spi4_rst(&mut self) -> SPI4_RST_W<PERIP_RST_EN0_SPEC> {
+        SPI4_RST_W::new(self, 31)
+    }
+}
+#[doc = "peripheral reset configuration register0\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_rst_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_rst_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PERIP_RST_EN0_SPEC;
+impl crate::RegisterSpec for PERIP_RST_EN0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perip_rst_en0::R`](R) reader structure"]
+impl crate::Readable for PERIP_RST_EN0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`perip_rst_en0::W`](W) writer structure"]
+impl crate::Writable for PERIP_RST_EN0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIP_RST_EN0 to value 0"]
+impl crate::Resettable for PERIP_RST_EN0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/perip_rst_en1.rs

@@ -0,0 +1,197 @@
+#[doc = "Register `PERIP_RST_EN1` reader"]
+pub type R = crate::R<PERIP_RST_EN1_SPEC>;
+#[doc = "Register `PERIP_RST_EN1` writer"]
+pub type W = crate::W<PERIP_RST_EN1_SPEC>;
+#[doc = "Field `PERI_BACKUP_RST` reader - Set 1 to let BACKUP reset"]
+pub type PERI_BACKUP_RST_R = crate::BitReader;
+#[doc = "Field `PERI_BACKUP_RST` writer - Set 1 to let BACKUP reset"]
+pub type PERI_BACKUP_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_AES_RST` reader - Set 1 to let CRYPTO_AES reset"]
+pub type CRYPTO_AES_RST_R = crate::BitReader;
+#[doc = "Field `CRYPTO_AES_RST` writer - Set 1 to let CRYPTO_AES reset"]
+pub type CRYPTO_AES_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_SHA_RST` reader - Set 1 to let CRYPTO_SHA reset"]
+pub type CRYPTO_SHA_RST_R = crate::BitReader;
+#[doc = "Field `CRYPTO_SHA_RST` writer - Set 1 to let CRYPTO_SHA reset"]
+pub type CRYPTO_SHA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_RSA_RST` reader - Set 1 to let CRYPTO_RSA reset"]
+pub type CRYPTO_RSA_RST_R = crate::BitReader;
+#[doc = "Field `CRYPTO_RSA_RST` writer - Set 1 to let CRYPTO_RSA reset"]
+pub type CRYPTO_RSA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_DS_RST` reader - Set 1 to let CRYPTO_DS reset"]
+pub type CRYPTO_DS_RST_R = crate::BitReader;
+#[doc = "Field `CRYPTO_DS_RST` writer - Set 1 to let CRYPTO_DS reset"]
+pub type CRYPTO_DS_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRYPTO_HMAC_RST` reader - Set 1 to let CRYPTO_HMAC reset"]
+pub type CRYPTO_HMAC_RST_R = crate::BitReader;
+#[doc = "Field `CRYPTO_HMAC_RST` writer - Set 1 to let CRYPTO_HMAC reset"]
+pub type CRYPTO_HMAC_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DMA_RST` reader - Set 1 to let DMA reset"]
+pub type DMA_RST_R = crate::BitReader;
+#[doc = "Field `DMA_RST` writer - Set 1 to let DMA reset"]
+pub type DMA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_HOST_RST` reader - Set 1 to let SDIO_HOST reset"]
+pub type SDIO_HOST_RST_R = crate::BitReader;
+#[doc = "Field `SDIO_HOST_RST` writer - Set 1 to let SDIO_HOST reset"]
+pub type SDIO_HOST_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LCD_CAM_RST` reader - Set 1 to let LCD_CAM reset"]
+pub type LCD_CAM_RST_R = crate::BitReader;
+#[doc = "Field `LCD_CAM_RST` writer - Set 1 to let LCD_CAM reset"]
+pub type LCD_CAM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART2_RST` reader - Set 1 to let UART2 reset"]
+pub type UART2_RST_R = crate::BitReader;
+#[doc = "Field `UART2_RST` writer - Set 1 to let UART2 reset"]
+pub type UART2_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_DEVICE_RST` reader - Set 1 to let USB_DEVICE reset"]
+pub type USB_DEVICE_RST_R = crate::BitReader;
+#[doc = "Field `USB_DEVICE_RST` writer - Set 1 to let USB_DEVICE reset"]
+pub type USB_DEVICE_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to let BACKUP reset"]
+    #[inline(always)]
+    pub fn peri_backup_rst(&self) -> PERI_BACKUP_RST_R {
+        PERI_BACKUP_RST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let CRYPTO_AES reset"]
+    #[inline(always)]
+    pub fn crypto_aes_rst(&self) -> CRYPTO_AES_RST_R {
+        CRYPTO_AES_RST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to let CRYPTO_SHA reset"]
+    #[inline(always)]
+    pub fn crypto_sha_rst(&self) -> CRYPTO_SHA_RST_R {
+        CRYPTO_SHA_RST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set 1 to let CRYPTO_RSA reset"]
+    #[inline(always)]
+    pub fn crypto_rsa_rst(&self) -> CRYPTO_RSA_RST_R {
+        CRYPTO_RSA_RST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set 1 to let CRYPTO_DS reset"]
+    #[inline(always)]
+    pub fn crypto_ds_rst(&self) -> CRYPTO_DS_RST_R {
+        CRYPTO_DS_RST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set 1 to let CRYPTO_HMAC reset"]
+    #[inline(always)]
+    pub fn crypto_hmac_rst(&self) -> CRYPTO_HMAC_RST_R {
+        CRYPTO_HMAC_RST_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set 1 to let DMA reset"]
+    #[inline(always)]
+    pub fn dma_rst(&self) -> DMA_RST_R {
+        DMA_RST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set 1 to let SDIO_HOST reset"]
+    #[inline(always)]
+    pub fn sdio_host_rst(&self) -> SDIO_HOST_RST_R {
+        SDIO_HOST_RST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set 1 to let LCD_CAM reset"]
+    #[inline(always)]
+    pub fn lcd_cam_rst(&self) -> LCD_CAM_RST_R {
+        LCD_CAM_RST_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Set 1 to let UART2 reset"]
+    #[inline(always)]
+    pub fn uart2_rst(&self) -> UART2_RST_R {
+        UART2_RST_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Set 1 to let USB_DEVICE reset"]
+    #[inline(always)]
+    pub fn usb_device_rst(&self) -> USB_DEVICE_RST_R {
+        USB_DEVICE_RST_R::new(((self.bits >> 10) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PERIP_RST_EN1")
+            .field("peri_backup_rst", &self.peri_backup_rst())
+            .field("crypto_aes_rst", &self.crypto_aes_rst())
+            .field("crypto_sha_rst", &self.crypto_sha_rst())
+            .field("crypto_rsa_rst", &self.crypto_rsa_rst())
+            .field("crypto_ds_rst", &self.crypto_ds_rst())
+            .field("crypto_hmac_rst", &self.crypto_hmac_rst())
+            .field("dma_rst", &self.dma_rst())
+            .field("sdio_host_rst", &self.sdio_host_rst())
+            .field("lcd_cam_rst", &self.lcd_cam_rst())
+            .field("uart2_rst", &self.uart2_rst())
+            .field("usb_device_rst", &self.usb_device_rst())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to let BACKUP reset"]
+    #[inline(always)]
+    pub fn peri_backup_rst(&mut self) -> PERI_BACKUP_RST_W<PERIP_RST_EN1_SPEC> {
+        PERI_BACKUP_RST_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to let CRYPTO_AES reset"]
+    #[inline(always)]
+    pub fn crypto_aes_rst(&mut self) -> CRYPTO_AES_RST_W<PERIP_RST_EN1_SPEC> {
+        CRYPTO_AES_RST_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to let CRYPTO_SHA reset"]
+    #[inline(always)]
+    pub fn crypto_sha_rst(&mut self) -> CRYPTO_SHA_RST_W<PERIP_RST_EN1_SPEC> {
+        CRYPTO_SHA_RST_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set 1 to let CRYPTO_RSA reset"]
+    #[inline(always)]
+    pub fn crypto_rsa_rst(&mut self) -> CRYPTO_RSA_RST_W<PERIP_RST_EN1_SPEC> {
+        CRYPTO_RSA_RST_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set 1 to let CRYPTO_DS reset"]
+    #[inline(always)]
+    pub fn crypto_ds_rst(&mut self) -> CRYPTO_DS_RST_W<PERIP_RST_EN1_SPEC> {
+        CRYPTO_DS_RST_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set 1 to let CRYPTO_HMAC reset"]
+    #[inline(always)]
+    pub fn crypto_hmac_rst(&mut self) -> CRYPTO_HMAC_RST_W<PERIP_RST_EN1_SPEC> {
+        CRYPTO_HMAC_RST_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set 1 to let DMA reset"]
+    #[inline(always)]
+    pub fn dma_rst(&mut self) -> DMA_RST_W<PERIP_RST_EN1_SPEC> {
+        DMA_RST_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set 1 to let SDIO_HOST reset"]
+    #[inline(always)]
+    pub fn sdio_host_rst(&mut self) -> SDIO_HOST_RST_W<PERIP_RST_EN1_SPEC> {
+        SDIO_HOST_RST_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set 1 to let LCD_CAM reset"]
+    #[inline(always)]
+    pub fn lcd_cam_rst(&mut self) -> LCD_CAM_RST_W<PERIP_RST_EN1_SPEC> {
+        LCD_CAM_RST_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set 1 to let UART2 reset"]
+    #[inline(always)]
+    pub fn uart2_rst(&mut self) -> UART2_RST_W<PERIP_RST_EN1_SPEC> {
+        UART2_RST_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Set 1 to let USB_DEVICE reset"]
+    #[inline(always)]
+    pub fn usb_device_rst(&mut self) -> USB_DEVICE_RST_W<PERIP_RST_EN1_SPEC> {
+        USB_DEVICE_RST_W::new(self, 10)
+    }
+}
+#[doc = "peripheral reset configuration regsiter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_rst_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_rst_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PERIP_RST_EN1_SPEC;
+impl crate::RegisterSpec for PERIP_RST_EN1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perip_rst_en1::R`](R) reader structure"]
+impl crate::Readable for PERIP_RST_EN1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`perip_rst_en1::W`](W) writer structure"]
+impl crate::Writable for PERIP_RST_EN1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIP_RST_EN1 to value 0x01fe"]
+impl crate::Resettable for PERIP_RST_EN1_SPEC {
+    const RESET_VALUE: u32 = 0x01fe;
+}

vendor/esp32s3/src/system/redundant_eco_ctrl.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `REDUNDANT_ECO_CTRL` reader"]
+pub type R = crate::R<REDUNDANT_ECO_CTRL_SPEC>;
+#[doc = "Register `REDUNDANT_ECO_CTRL` writer"]
+pub type W = crate::W<REDUNDANT_ECO_CTRL_SPEC>;
+#[doc = "Field `REDUNDANT_ECO_DRIVE` reader - ******* Description ***********"]
+pub type REDUNDANT_ECO_DRIVE_R = crate::BitReader;
+#[doc = "Field `REDUNDANT_ECO_DRIVE` writer - ******* Description ***********"]
+pub type REDUNDANT_ECO_DRIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `REDUNDANT_ECO_RESULT` reader - ******* Description ***********"]
+pub type REDUNDANT_ECO_RESULT_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn redundant_eco_drive(&self) -> REDUNDANT_ECO_DRIVE_R {
+        REDUNDANT_ECO_DRIVE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn redundant_eco_result(&self) -> REDUNDANT_ECO_RESULT_R {
+        REDUNDANT_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("REDUNDANT_ECO_CTRL")
+            .field("redundant_eco_drive", &self.redundant_eco_drive())
+            .field("redundant_eco_result", &self.redundant_eco_result())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn redundant_eco_drive(&mut self) -> REDUNDANT_ECO_DRIVE_W<REDUNDANT_ECO_CTRL_SPEC> {
+        REDUNDANT_ECO_DRIVE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`redundant_eco_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`redundant_eco_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct REDUNDANT_ECO_CTRL_SPEC;
+impl crate::RegisterSpec for REDUNDANT_ECO_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`redundant_eco_ctrl::R`](R) reader structure"]
+impl crate::Readable for REDUNDANT_ECO_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`redundant_eco_ctrl::W`](W) writer structure"]
+impl crate::Writable for REDUNDANT_ECO_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets REDUNDANT_ECO_CTRL to value 0"]
+impl crate::Resettable for REDUNDANT_ECO_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/rsa_pd_ctrl.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `RSA_PD_CTRL` reader"]
+pub type R = crate::R<RSA_PD_CTRL_SPEC>;
+#[doc = "Register `RSA_PD_CTRL` writer"]
+pub type W = crate::W<RSA_PD_CTRL_SPEC>;
+#[doc = "Field `RSA_MEM_PD` reader - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid."]
+pub type RSA_MEM_PD_R = crate::BitReader;
+#[doc = "Field `RSA_MEM_PD` writer - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid."]
+pub type RSA_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RSA_MEM_FORCE_PU` reader - Set 1 to force power up RSA memory, this bit has the second highest priority."]
+pub type RSA_MEM_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `RSA_MEM_FORCE_PU` writer - Set 1 to force power up RSA memory, this bit has the second highest priority."]
+pub type RSA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RSA_MEM_FORCE_PD` reader - Set 1 to force power down RSA memory,this bit has the highest priority."]
+pub type RSA_MEM_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `RSA_MEM_FORCE_PD` writer - Set 1 to force power down RSA memory,this bit has the highest priority."]
+pub type RSA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid."]
+    #[inline(always)]
+    pub fn rsa_mem_pd(&self) -> RSA_MEM_PD_R {
+        RSA_MEM_PD_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set 1 to force power up RSA memory, this bit has the second highest priority."]
+    #[inline(always)]
+    pub fn rsa_mem_force_pu(&self) -> RSA_MEM_FORCE_PU_R {
+        RSA_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set 1 to force power down RSA memory,this bit has the highest priority."]
+    #[inline(always)]
+    pub fn rsa_mem_force_pd(&self) -> RSA_MEM_FORCE_PD_R {
+        RSA_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RSA_PD_CTRL")
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid."]
+    #[inline(always)]
+    pub fn rsa_mem_pd(&mut self) -> RSA_MEM_PD_W<RSA_PD_CTRL_SPEC> {
+        RSA_MEM_PD_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set 1 to force power up RSA memory, this bit has the second highest priority."]
+    #[inline(always)]
+    pub fn rsa_mem_force_pu(&mut self) -> RSA_MEM_FORCE_PU_W<RSA_PD_CTRL_SPEC> {
+        RSA_MEM_FORCE_PU_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set 1 to force power down RSA memory,this bit has the highest priority."]
+    #[inline(always)]
+    pub fn rsa_mem_force_pd(&mut self) -> RSA_MEM_FORCE_PD_W<RSA_PD_CTRL_SPEC> {
+        RSA_MEM_FORCE_PD_W::new(self, 2)
+    }
+}
+#[doc = "rsa memory power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rsa_pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rsa_pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RSA_PD_CTRL_SPEC;
+impl crate::RegisterSpec for RSA_PD_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rsa_pd_ctrl::R`](R) reader structure"]
+impl crate::Readable for RSA_PD_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rsa_pd_ctrl::W`](W) writer structure"]
+impl crate::Writable for RSA_PD_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RSA_PD_CTRL to value 0x01"]
+impl crate::Resettable for RSA_PD_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/system/rtc_fastmem_config.rs

@@ -0,0 +1,85 @@
+#[doc = "Register `RTC_FASTMEM_CONFIG` reader"]
+pub type R = crate::R<RTC_FASTMEM_CONFIG_SPEC>;
+#[doc = "Register `RTC_FASTMEM_CONFIG` writer"]
+pub type W = crate::W<RTC_FASTMEM_CONFIG_SPEC>;
+#[doc = "Field `RTC_MEM_CRC_START` reader - Set 1 to start the CRC of RTC memory"]
+pub type RTC_MEM_CRC_START_R = crate::BitReader;
+#[doc = "Field `RTC_MEM_CRC_START` writer - Set 1 to start the CRC of RTC memory"]
+pub type RTC_MEM_CRC_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RTC_MEM_CRC_ADDR` reader - This field is used to set address of RTC memory for CRC."]
+pub type RTC_MEM_CRC_ADDR_R = crate::FieldReader<u16>;
+#[doc = "Field `RTC_MEM_CRC_ADDR` writer - This field is used to set address of RTC memory for CRC."]
+pub type RTC_MEM_CRC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `RTC_MEM_CRC_LEN` reader - This field is used to set length of RTC memory for CRC based on start address."]
+pub type RTC_MEM_CRC_LEN_R = crate::FieldReader<u16>;
+#[doc = "Field `RTC_MEM_CRC_LEN` writer - This field is used to set length of RTC memory for CRC based on start address."]
+pub type RTC_MEM_CRC_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `RTC_MEM_CRC_FINISH` reader - This bit stores the status of RTC memory CRC.1 means finished."]
+pub type RTC_MEM_CRC_FINISH_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 8 - Set 1 to start the CRC of RTC memory"]
+    #[inline(always)]
+    pub fn rtc_mem_crc_start(&self) -> RTC_MEM_CRC_START_R {
+        RTC_MEM_CRC_START_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bits 9:19 - This field is used to set address of RTC memory for CRC."]
+    #[inline(always)]
+    pub fn rtc_mem_crc_addr(&self) -> RTC_MEM_CRC_ADDR_R {
+        RTC_MEM_CRC_ADDR_R::new(((self.bits >> 9) & 0x07ff) as u16)
+    }
+    #[doc = "Bits 20:30 - This field is used to set length of RTC memory for CRC based on start address."]
+    #[inline(always)]
+    pub fn rtc_mem_crc_len(&self) -> RTC_MEM_CRC_LEN_R {
+        RTC_MEM_CRC_LEN_R::new(((self.bits >> 20) & 0x07ff) as u16)
+    }
+    #[doc = "Bit 31 - This bit stores the status of RTC memory CRC.1 means finished."]
+    #[inline(always)]
+    pub fn rtc_mem_crc_finish(&self) -> RTC_MEM_CRC_FINISH_R {
+        RTC_MEM_CRC_FINISH_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_FASTMEM_CONFIG")
+            .field("rtc_mem_crc_start", &self.rtc_mem_crc_start())
+            .field("rtc_mem_crc_addr", &self.rtc_mem_crc_addr())
+            .field("rtc_mem_crc_len", &self.rtc_mem_crc_len())
+            .field("rtc_mem_crc_finish", &self.rtc_mem_crc_finish())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 8 - Set 1 to start the CRC of RTC memory"]
+    #[inline(always)]
+    pub fn rtc_mem_crc_start(&mut self) -> RTC_MEM_CRC_START_W<RTC_FASTMEM_CONFIG_SPEC> {
+        RTC_MEM_CRC_START_W::new(self, 8)
+    }
+    #[doc = "Bits 9:19 - This field is used to set address of RTC memory for CRC."]
+    #[inline(always)]
+    pub fn rtc_mem_crc_addr(&mut self) -> RTC_MEM_CRC_ADDR_W<RTC_FASTMEM_CONFIG_SPEC> {
+        RTC_MEM_CRC_ADDR_W::new(self, 9)
+    }
+    #[doc = "Bits 20:30 - This field is used to set length of RTC memory for CRC based on start address."]
+    #[inline(always)]
+    pub fn rtc_mem_crc_len(&mut self) -> RTC_MEM_CRC_LEN_W<RTC_FASTMEM_CONFIG_SPEC> {
+        RTC_MEM_CRC_LEN_W::new(self, 20)
+    }
+}
+#[doc = "RTC fast memory configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_fastmem_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_fastmem_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_FASTMEM_CONFIG_SPEC;
+impl crate::RegisterSpec for RTC_FASTMEM_CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_fastmem_config::R`](R) reader structure"]
+impl crate::Readable for RTC_FASTMEM_CONFIG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_fastmem_config::W`](W) writer structure"]
+impl crate::Writable for RTC_FASTMEM_CONFIG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_FASTMEM_CONFIG to value 0x7ff0_0000"]
+impl crate::Resettable for RTC_FASTMEM_CONFIG_SPEC {
+    const RESET_VALUE: u32 = 0x7ff0_0000;
+}

vendor/esp32s3/src/system/rtc_fastmem_crc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RTC_FASTMEM_CRC` reader"]
+pub type R = crate::R<RTC_FASTMEM_CRC_SPEC>;
+#[doc = "Field `RTC_MEM_CRC_RES` reader - This field stores the CRC result of RTC memory."]
+pub type RTC_MEM_CRC_RES_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This field stores the CRC result of RTC memory."]
+    #[inline(always)]
+    pub fn rtc_mem_crc_res(&self) -> RTC_MEM_CRC_RES_R {
+        RTC_MEM_CRC_RES_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_FASTMEM_CRC")
+            .field("rtc_mem_crc_res", &self.rtc_mem_crc_res())
+            .finish()
+    }
+}
+#[doc = "RTC fast memory CRC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_fastmem_crc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_FASTMEM_CRC_SPEC;
+impl crate::RegisterSpec for RTC_FASTMEM_CRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_fastmem_crc::R`](R) reader structure"]
+impl crate::Readable for RTC_FASTMEM_CRC_SPEC {}
+#[doc = "`reset()` method sets RTC_FASTMEM_CRC to value 0"]
+impl crate::Resettable for RTC_FASTMEM_CRC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/system/sysclk_conf.rs

@@ -0,0 +1,78 @@
+#[doc = "Register `SYSCLK_CONF` reader"]
+pub type R = crate::R<SYSCLK_CONF_SPEC>;
+#[doc = "Register `SYSCLK_CONF` writer"]
+pub type W = crate::W<SYSCLK_CONF_SPEC>;
+#[doc = "Field `PRE_DIV_CNT` reader - This field is used to set the count of prescaler of XTAL_CLK."]
+pub type PRE_DIV_CNT_R = crate::FieldReader<u16>;
+#[doc = "Field `PRE_DIV_CNT` writer - This field is used to set the count of prescaler of XTAL_CLK."]
+pub type PRE_DIV_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `SOC_CLK_SEL` reader - This field is used to select soc clock."]
+pub type SOC_CLK_SEL_R = crate::FieldReader;
+#[doc = "Field `SOC_CLK_SEL` writer - This field is used to select soc clock."]
+pub type SOC_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `CLK_XTAL_FREQ` reader - This field is used to read xtal frequency in MHz."]
+pub type CLK_XTAL_FREQ_R = crate::FieldReader;
+#[doc = "Field `CLK_DIV_EN` reader - Reserved."]
+pub type CLK_DIV_EN_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL_CLK."]
+    #[inline(always)]
+    pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R {
+        PRE_DIV_CNT_R::new((self.bits & 0x03ff) as u16)
+    }
+    #[doc = "Bits 10:11 - This field is used to select soc clock."]
+    #[inline(always)]
+    pub fn soc_clk_sel(&self) -> SOC_CLK_SEL_R {
+        SOC_CLK_SEL_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    #[doc = "Bits 12:18 - This field is used to read xtal frequency in MHz."]
+    #[inline(always)]
+    pub fn clk_xtal_freq(&self) -> CLK_XTAL_FREQ_R {
+        CLK_XTAL_FREQ_R::new(((self.bits >> 12) & 0x7f) as u8)
+    }
+    #[doc = "Bit 19 - Reserved."]
+    #[inline(always)]
+    pub fn clk_div_en(&self) -> CLK_DIV_EN_R {
+        CLK_DIV_EN_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SYSCLK_CONF")
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
+            .field("clk_div_en", &self.clk_div_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL_CLK."]
+    #[inline(always)]
+    pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
+        PRE_DIV_CNT_W::new(self, 0)
+    }
+    #[doc = "Bits 10:11 - This field is used to select soc clock."]
+    #[inline(always)]
+    pub fn soc_clk_sel(&mut self) -> SOC_CLK_SEL_W<SYSCLK_CONF_SPEC> {
+        SOC_CLK_SEL_W::new(self, 10)
+    }
+}
+#[doc = "System clock configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SYSCLK_CONF_SPEC;
+impl crate::RegisterSpec for SYSCLK_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sysclk_conf::R`](R) reader structure"]
+impl crate::Readable for SYSCLK_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sysclk_conf::W`](W) writer structure"]
+impl crate::Writable for SYSCLK_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SYSCLK_CONF to value 0x01"]
+impl crate::Resettable for SYSCLK_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}