swaits
46822c182c
First RP2040 board and third MCU family (after ESP32-S3 and nRF52840). Hardware: RP2040 + SX1262 radio, 850-930 MHz HF, PE4259 antenna switch, LED on GPIO25, no OLED, USB-C via FPC ribbon cable to adapter board. New files: - src/hal/rp2040.rs: MCU primitives (SPI bus, USB driver, flash unique ID MAC) - src/board/waveshare_rp2040_lora.rs: board implementation - ld/rp2040-memory.x: linker memory layout Also fixes cortex-m-rt/set-vtor (moved from global dep to per-board feature, since Cortex-M0+ has no VTOR register) and makes build.rs memory.x selection target-aware.
25 lines
595 B
Plaintext
25 lines
595 B
Plaintext
/* RP2040 memory layout — UF2 bootloader (ROM boot2)
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*
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* 0x10000000 – 0x10000100 boot2 (second-stage bootloader, 256 bytes)
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* 0x10000100 – 0x10200000 Application <- we live here
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*
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* Flash: 2MB (W25Q16JV on Waveshare RP2040-LoRa)
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* RAM: 264KB SRAM (two 256KB banks + 2x 4KB scratch)
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*/
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MEMORY
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{
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BOOT2 : ORIGIN = 0x10000000, LENGTH = 0x100
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FLASH : ORIGIN = 0x10000100, LENGTH = 2048K - 0x100
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RAM : ORIGIN = 0x20000000, LENGTH = 264K
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}
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EXTERN(BOOT2_FIRMWARE)
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SECTIONS {
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.boot2 ORIGIN(BOOT2) :
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{
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KEEP(*(.boot2));
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} > BOOT2
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} INSERT BEFORE .text;
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