feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/extmem/cache_acs_cnt_clr.rs

@@ -0,0 +1,39 @@
+#[doc = "Register `CACHE_ACS_CNT_CLR` writer"]
+pub type W = crate::W<CACHE_ACS_CNT_CLR_SPEC>;
+#[doc = "Field `DCACHE_ACS_CNT_CLR` writer - The bit is used to clear dcache counter."]
+pub type DCACHE_ACS_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_ACS_CNT_CLR` writer - The bit is used to clear icache counter."]
+pub type ICACHE_ACS_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CACHE_ACS_CNT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to clear dcache counter."]
+    #[inline(always)]
+    pub fn dcache_acs_cnt_clr(&mut self) -> DCACHE_ACS_CNT_CLR_W<CACHE_ACS_CNT_CLR_SPEC> {
+        DCACHE_ACS_CNT_CLR_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to clear icache counter."]
+    #[inline(always)]
+    pub fn icache_acs_cnt_clr(&mut self) -> ICACHE_ACS_CNT_CLR_W<CACHE_ACS_CNT_CLR_SPEC> {
+        ICACHE_ACS_CNT_CLR_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_acs_cnt_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_ACS_CNT_CLR_SPEC;
+impl crate::RegisterSpec for CACHE_ACS_CNT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`cache_acs_cnt_clr::W`](W) writer structure"]
+impl crate::Writable for CACHE_ACS_CNT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_ACS_CNT_CLR to value 0"]
+impl crate::Resettable for CACHE_ACS_CNT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CACHE_BRIDGE_ARBITER_CTRL` reader"]
+pub type R = crate::R<CACHE_BRIDGE_ARBITER_CTRL_SPEC>;
+#[doc = "Register `CACHE_BRIDGE_ARBITER_CTRL` writer"]
+pub type W = crate::W<CACHE_BRIDGE_ARBITER_CTRL_SPEC>;
+#[doc = "Field `ALLOC_WB_HOLD_ARBITER` reader - Reserved"]
+pub type ALLOC_WB_HOLD_ARBITER_R = crate::BitReader;
+#[doc = "Field `ALLOC_WB_HOLD_ARBITER` writer - Reserved"]
+pub type ALLOC_WB_HOLD_ARBITER_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Reserved"]
+    #[inline(always)]
+    pub fn alloc_wb_hold_arbiter(&self) -> ALLOC_WB_HOLD_ARBITER_R {
+        ALLOC_WB_HOLD_ARBITER_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_BRIDGE_ARBITER_CTRL")
+            .field("alloc_wb_hold_arbiter", &self.alloc_wb_hold_arbiter())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Reserved"]
+    #[inline(always)]
+    pub fn alloc_wb_hold_arbiter(
+        &mut self,
+    ) -> ALLOC_WB_HOLD_ARBITER_W<CACHE_BRIDGE_ARBITER_CTRL_SPEC> {
+        ALLOC_WB_HOLD_ARBITER_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_bridge_arbiter_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_bridge_arbiter_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_BRIDGE_ARBITER_CTRL_SPEC;
+impl crate::RegisterSpec for CACHE_BRIDGE_ARBITER_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_bridge_arbiter_ctrl::R`](R) reader structure"]
+impl crate::Readable for CACHE_BRIDGE_ARBITER_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_bridge_arbiter_ctrl::W`](W) writer structure"]
+impl crate::Writable for CACHE_BRIDGE_ARBITER_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_BRIDGE_ARBITER_CTRL to value 0"]
+impl crate::Resettable for CACHE_BRIDGE_ARBITER_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_conf_misc.rs

@@ -0,0 +1,87 @@
+#[doc = "Register `CACHE_CONF_MISC` reader"]
+pub type R = crate::R<CACHE_CONF_MISC_SPEC>;
+#[doc = "Register `CACHE_CONF_MISC` writer"]
+pub type W = crate::W<CACHE_CONF_MISC_SPEC>;
+#[doc = "Field `CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT` reader - The bit is used to disable checking mmu entry fault by preload operation."]
+pub type CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_R = crate::BitReader;
+#[doc = "Field `CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT` writer - The bit is used to disable checking mmu entry fault by preload operation."]
+pub type CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT` reader - The bit is used to disable checking mmu entry fault by sync operation."]
+pub type CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_R = crate::BitReader;
+#[doc = "Field `CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT` writer - The bit is used to disable checking mmu entry fault by sync operation."]
+pub type CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CACHE_TRACE_ENA` reader - The bit is used to enable cache trace function."]
+pub type CACHE_TRACE_ENA_R = crate::BitReader;
+#[doc = "Field `CACHE_TRACE_ENA` writer - The bit is used to enable cache trace function."]
+pub type CACHE_TRACE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
+    #[inline(always)]
+    pub fn cache_ignore_preload_mmu_entry_fault(&self) -> CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_R {
+        CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to disable checking mmu entry fault by sync operation."]
+    #[inline(always)]
+    pub fn cache_ignore_sync_mmu_entry_fault(&self) -> CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_R {
+        CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable cache trace function."]
+    #[inline(always)]
+    pub fn cache_trace_ena(&self) -> CACHE_TRACE_ENA_R {
+        CACHE_TRACE_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_CONF_MISC")
+            .field(
+                "cache_ignore_preload_mmu_entry_fault",
+                &self.cache_ignore_preload_mmu_entry_fault(),
+            )
+            .field(
+                "cache_ignore_sync_mmu_entry_fault",
+                &self.cache_ignore_sync_mmu_entry_fault(),
+            )
+            .field("cache_trace_ena", &self.cache_trace_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
+    #[inline(always)]
+    pub fn cache_ignore_preload_mmu_entry_fault(
+        &mut self,
+    ) -> CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
+        CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to disable checking mmu entry fault by sync operation."]
+    #[inline(always)]
+    pub fn cache_ignore_sync_mmu_entry_fault(
+        &mut self,
+    ) -> CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
+        CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable cache trace function."]
+    #[inline(always)]
+    pub fn cache_trace_ena(&mut self) -> CACHE_TRACE_ENA_W<CACHE_CONF_MISC_SPEC> {
+        CACHE_TRACE_ENA_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_conf_misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_conf_misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_CONF_MISC_SPEC;
+impl crate::RegisterSpec for CACHE_CONF_MISC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_conf_misc::R`](R) reader structure"]
+impl crate::Readable for CACHE_CONF_MISC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_conf_misc::W`](W) writer structure"]
+impl crate::Writable for CACHE_CONF_MISC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_CONF_MISC to value 0x07"]
+impl crate::Resettable for CACHE_CONF_MISC_SPEC {
+    const RESET_VALUE: u32 = 0x07;
+}

vendor/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs

@@ -0,0 +1,86 @@
+#[doc = "Register `CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON` reader"]
+pub type R = crate::R<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC>;
+#[doc = "Register `CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON` writer"]
+pub type W = crate::W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC>;
+#[doc = "Field `CLK_FORCE_ON_MANUAL_CRYPT` reader - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
+pub type CLK_FORCE_ON_MANUAL_CRYPT_R = crate::BitReader;
+#[doc = "Field `CLK_FORCE_ON_MANUAL_CRYPT` writer - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
+pub type CLK_FORCE_ON_MANUAL_CRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_FORCE_ON_AUTO_CRYPT` reader - The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating."]
+pub type CLK_FORCE_ON_AUTO_CRYPT_R = crate::BitReader;
+#[doc = "Field `CLK_FORCE_ON_AUTO_CRYPT` writer - The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating."]
+pub type CLK_FORCE_ON_AUTO_CRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_FORCE_ON_CRYPT` reader - The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating."]
+pub type CLK_FORCE_ON_CRYPT_R = crate::BitReader;
+#[doc = "Field `CLK_FORCE_ON_CRYPT` writer - The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating."]
+pub type CLK_FORCE_ON_CRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn clk_force_on_manual_crypt(&self) -> CLK_FORCE_ON_MANUAL_CRYPT_R {
+        CLK_FORCE_ON_MANUAL_CRYPT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn clk_force_on_auto_crypt(&self) -> CLK_FORCE_ON_AUTO_CRYPT_R {
+        CLK_FORCE_ON_AUTO_CRYPT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn clk_force_on_crypt(&self) -> CLK_FORCE_ON_CRYPT_R {
+        CLK_FORCE_ON_CRYPT_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON")
+            .field(
+                "clk_force_on_manual_crypt",
+                &self.clk_force_on_manual_crypt(),
+            )
+            .field("clk_force_on_auto_crypt", &self.clk_force_on_auto_crypt())
+            .field("clk_force_on_crypt", &self.clk_force_on_crypt())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn clk_force_on_manual_crypt(
+        &mut self,
+    ) -> CLK_FORCE_ON_MANUAL_CRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
+        CLK_FORCE_ON_MANUAL_CRYPT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn clk_force_on_auto_crypt(
+        &mut self,
+    ) -> CLK_FORCE_ON_AUTO_CRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
+        CLK_FORCE_ON_AUTO_CRYPT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn clk_force_on_crypt(
+        &mut self,
+    ) -> CLK_FORCE_ON_CRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
+        CLK_FORCE_ON_CRYPT_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_encrypt_decrypt_clk_force_on::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_encrypt_decrypt_clk_force_on::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC;
+impl crate::RegisterSpec for CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_encrypt_decrypt_clk_force_on::R`](R) reader structure"]
+impl crate::Readable for CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_encrypt_decrypt_clk_force_on::W`](W) writer structure"]
+impl crate::Writable for CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON to value 0x07"]
+impl crate::Resettable for CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC {
+    const RESET_VALUE: u32 = 0x07;
+}

vendor/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE` reader"]
+pub type R = crate::R<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC>;
+#[doc = "Register `CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE` writer"]
+pub type W = crate::W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC>;
+#[doc = "Field `RECORD_DISABLE_DB_ENCRYPT` reader - Reserved"]
+pub type RECORD_DISABLE_DB_ENCRYPT_R = crate::BitReader;
+#[doc = "Field `RECORD_DISABLE_DB_ENCRYPT` writer - Reserved"]
+pub type RECORD_DISABLE_DB_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RECORD_DISABLE_G0CB_DECRYPT` reader - Reserved"]
+pub type RECORD_DISABLE_G0CB_DECRYPT_R = crate::BitReader;
+#[doc = "Field `RECORD_DISABLE_G0CB_DECRYPT` writer - Reserved"]
+pub type RECORD_DISABLE_G0CB_DECRYPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Reserved"]
+    #[inline(always)]
+    pub fn record_disable_db_encrypt(&self) -> RECORD_DISABLE_DB_ENCRYPT_R {
+        RECORD_DISABLE_DB_ENCRYPT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Reserved"]
+    #[inline(always)]
+    pub fn record_disable_g0cb_decrypt(&self) -> RECORD_DISABLE_G0CB_DECRYPT_R {
+        RECORD_DISABLE_G0CB_DECRYPT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE")
+            .field(
+                "record_disable_db_encrypt",
+                &self.record_disable_db_encrypt(),
+            )
+            .field(
+                "record_disable_g0cb_decrypt",
+                &self.record_disable_g0cb_decrypt(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Reserved"]
+    #[inline(always)]
+    pub fn record_disable_db_encrypt(
+        &mut self,
+    ) -> RECORD_DISABLE_DB_ENCRYPT_W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
+        RECORD_DISABLE_DB_ENCRYPT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Reserved"]
+    #[inline(always)]
+    pub fn record_disable_g0cb_decrypt(
+        &mut self,
+    ) -> RECORD_DISABLE_G0CB_DECRYPT_W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
+        RECORD_DISABLE_G0CB_DECRYPT_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_encrypt_decrypt_record_disable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_encrypt_decrypt_record_disable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC;
+impl crate::RegisterSpec for CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_encrypt_decrypt_record_disable::R`](R) reader structure"]
+impl crate::Readable for CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_encrypt_decrypt_record_disable::W`](W) writer structure"]
+impl crate::Writable for CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE to value 0"]
+impl crate::Resettable for CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_ilg_int_clr.rs

@@ -0,0 +1,88 @@
+#[doc = "Register `CACHE_ILG_INT_CLR` writer"]
+pub type W = crate::W<CACHE_ILG_INT_CLR_SPEC>;
+#[doc = "Field `ICACHE_SYNC_OP_FAULT` writer - The bit is used to clear interrupt by sync configurations fault."]
+pub type ICACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` writer - The bit is used to clear interrupt by preload configurations fault."]
+pub type ICACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DCACHE_SYNC_OP_FAULT` writer - The bit is used to clear interrupt by sync configurations fault."]
+pub type DCACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` writer - The bit is used to clear interrupt by preload configurations fault."]
+pub type DCACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DCACHE_WRITE_FLASH` writer - The bit is used to clear interrupt by dcache trying to write flash."]
+pub type DCACHE_WRITE_FLASH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `MMU_ENTRY_FAULT` writer - The bit is used to clear interrupt by mmu entry fault."]
+pub type MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DCACHE_OCCUPY_EXC` writer - The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+pub type DCACHE_OCCUPY_EXC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `IBUS_CNT_OVF` writer - The bit is used to clear interrupt by ibus counter overflow."]
+pub type IBUS_CNT_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DBUS_CNT_OVF` writer - The bit is used to clear interrupt by dbus counter overflow."]
+pub type DBUS_CNT_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to clear interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
+        ICACHE_SYNC_OP_FAULT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to clear interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
+        ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to clear interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn dcache_sync_op_fault(&mut self) -> DCACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
+        DCACHE_SYNC_OP_FAULT_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to clear interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn dcache_preload_op_fault(&mut self) -> DCACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
+        DCACHE_PRELOAD_OP_FAULT_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The bit is used to clear interrupt by dcache trying to write flash."]
+    #[inline(always)]
+    pub fn dcache_write_flash(&mut self) -> DCACHE_WRITE_FLASH_W<CACHE_ILG_INT_CLR_SPEC> {
+        DCACHE_WRITE_FLASH_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The bit is used to clear interrupt by mmu entry fault."]
+    #[inline(always)]
+    pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
+        MMU_ENTRY_FAULT_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+    #[inline(always)]
+    pub fn dcache_occupy_exc(&mut self) -> DCACHE_OCCUPY_EXC_W<CACHE_ILG_INT_CLR_SPEC> {
+        DCACHE_OCCUPY_EXC_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The bit is used to clear interrupt by ibus counter overflow."]
+    #[inline(always)]
+    pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_CLR_SPEC> {
+        IBUS_CNT_OVF_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - The bit is used to clear interrupt by dbus counter overflow."]
+    #[inline(always)]
+    pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_CLR_SPEC> {
+        DBUS_CNT_OVF_W::new(self, 8)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_ILG_INT_CLR_SPEC;
+impl crate::RegisterSpec for CACHE_ILG_INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`cache_ilg_int_clr::W`](W) writer structure"]
+impl crate::Writable for CACHE_ILG_INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
+}
+#[doc = "`reset()` method sets CACHE_ILG_INT_CLR to value 0"]
+impl crate::Resettable for CACHE_ILG_INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_ilg_int_ena.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `CACHE_ILG_INT_ENA` reader"]
+pub type R = crate::R<CACHE_ILG_INT_ENA_SPEC>;
+#[doc = "Register `CACHE_ILG_INT_ENA` writer"]
+pub type W = crate::W<CACHE_ILG_INT_ENA_SPEC>;
+#[doc = "Field `ICACHE_SYNC_OP_FAULT` reader - The bit is used to enable interrupt by sync configurations fault."]
+pub type ICACHE_SYNC_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `ICACHE_SYNC_OP_FAULT` writer - The bit is used to enable interrupt by sync configurations fault."]
+pub type ICACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` reader - The bit is used to enable interrupt by preload configurations fault."]
+pub type ICACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` writer - The bit is used to enable interrupt by preload configurations fault."]
+pub type ICACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_SYNC_OP_FAULT` reader - The bit is used to enable interrupt by sync configurations fault."]
+pub type DCACHE_SYNC_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `DCACHE_SYNC_OP_FAULT` writer - The bit is used to enable interrupt by sync configurations fault."]
+pub type DCACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` reader - The bit is used to enable interrupt by preload configurations fault."]
+pub type DCACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` writer - The bit is used to enable interrupt by preload configurations fault."]
+pub type DCACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_WRITE_FLASH` reader - The bit is used to enable interrupt by dcache trying to write flash."]
+pub type DCACHE_WRITE_FLASH_R = crate::BitReader;
+#[doc = "Field `DCACHE_WRITE_FLASH` writer - The bit is used to enable interrupt by dcache trying to write flash."]
+pub type DCACHE_WRITE_FLASH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MMU_ENTRY_FAULT` reader - The bit is used to enable interrupt by mmu entry fault."]
+pub type MMU_ENTRY_FAULT_R = crate::BitReader;
+#[doc = "Field `MMU_ENTRY_FAULT` writer - The bit is used to enable interrupt by mmu entry fault."]
+pub type MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_OCCUPY_EXC` reader - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+pub type DCACHE_OCCUPY_EXC_R = crate::BitReader;
+#[doc = "Field `DCACHE_OCCUPY_EXC` writer - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+pub type DCACHE_OCCUPY_EXC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IBUS_CNT_OVF` reader - The bit is used to enable interrupt by ibus counter overflow."]
+pub type IBUS_CNT_OVF_R = crate::BitReader;
+#[doc = "Field `IBUS_CNT_OVF` writer - The bit is used to enable interrupt by ibus counter overflow."]
+pub type IBUS_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DBUS_CNT_OVF` reader - The bit is used to enable interrupt by dbus counter overflow."]
+pub type DBUS_CNT_OVF_R = crate::BitReader;
+#[doc = "Field `DBUS_CNT_OVF` writer - The bit is used to enable interrupt by dbus counter overflow."]
+pub type DBUS_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn icache_sync_op_fault(&self) -> ICACHE_SYNC_OP_FAULT_R {
+        ICACHE_SYNC_OP_FAULT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn icache_preload_op_fault(&self) -> ICACHE_PRELOAD_OP_FAULT_R {
+        ICACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn dcache_sync_op_fault(&self) -> DCACHE_SYNC_OP_FAULT_R {
+        DCACHE_SYNC_OP_FAULT_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to enable interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn dcache_preload_op_fault(&self) -> DCACHE_PRELOAD_OP_FAULT_R {
+        DCACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to enable interrupt by dcache trying to write flash."]
+    #[inline(always)]
+    pub fn dcache_write_flash(&self) -> DCACHE_WRITE_FLASH_R {
+        DCACHE_WRITE_FLASH_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
+    #[inline(always)]
+    pub fn mmu_entry_fault(&self) -> MMU_ENTRY_FAULT_R {
+        MMU_ENTRY_FAULT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+    #[inline(always)]
+    pub fn dcache_occupy_exc(&self) -> DCACHE_OCCUPY_EXC_R {
+        DCACHE_OCCUPY_EXC_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
+    #[inline(always)]
+    pub fn ibus_cnt_ovf(&self) -> IBUS_CNT_OVF_R {
+        IBUS_CNT_OVF_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
+    #[inline(always)]
+    pub fn dbus_cnt_ovf(&self) -> DBUS_CNT_OVF_R {
+        DBUS_CNT_OVF_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_ILG_INT_ENA")
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("dcache_sync_op_fault", &self.dcache_sync_op_fault())
+            .field("dcache_preload_op_fault", &self.dcache_preload_op_fault())
+            .field("dcache_write_flash", &self.dcache_write_flash())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("dcache_occupy_exc", &self.dcache_occupy_exc())
+            .field("ibus_cnt_ovf", &self.ibus_cnt_ovf())
+            .field("dbus_cnt_ovf", &self.dbus_cnt_ovf())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
+        ICACHE_SYNC_OP_FAULT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
+        ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn dcache_sync_op_fault(&mut self) -> DCACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
+        DCACHE_SYNC_OP_FAULT_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to enable interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn dcache_preload_op_fault(&mut self) -> DCACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
+        DCACHE_PRELOAD_OP_FAULT_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The bit is used to enable interrupt by dcache trying to write flash."]
+    #[inline(always)]
+    pub fn dcache_write_flash(&mut self) -> DCACHE_WRITE_FLASH_W<CACHE_ILG_INT_ENA_SPEC> {
+        DCACHE_WRITE_FLASH_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
+    #[inline(always)]
+    pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
+        MMU_ENTRY_FAULT_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+    #[inline(always)]
+    pub fn dcache_occupy_exc(&mut self) -> DCACHE_OCCUPY_EXC_W<CACHE_ILG_INT_ENA_SPEC> {
+        DCACHE_OCCUPY_EXC_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
+    #[inline(always)]
+    pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
+        IBUS_CNT_OVF_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
+    #[inline(always)]
+    pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
+        DBUS_CNT_OVF_W::new(self, 8)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_ILG_INT_ENA_SPEC;
+impl crate::RegisterSpec for CACHE_ILG_INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_ilg_int_ena::R`](R) reader structure"]
+impl crate::Readable for CACHE_ILG_INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_ilg_int_ena::W`](W) writer structure"]
+impl crate::Writable for CACHE_ILG_INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_ILG_INT_ENA to value 0"]
+impl crate::Resettable for CACHE_ILG_INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_ilg_int_st.rs

@@ -0,0 +1,124 @@
+#[doc = "Register `CACHE_ILG_INT_ST` reader"]
+pub type R = crate::R<CACHE_ILG_INT_ST_SPEC>;
+#[doc = "Field `ICACHE_SYNC_OP_FAULT` reader - The bit is used to indicate interrupt by sync configurations fault."]
+pub type ICACHE_SYNC_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` reader - The bit is used to indicate interrupt by preload configurations fault."]
+pub type ICACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `DCACHE_SYNC_OP_FAULT` reader - The bit is used to indicate interrupt by sync configurations fault."]
+pub type DCACHE_SYNC_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` reader - The bit is used to indicate interrupt by preload configurations fault."]
+pub type DCACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
+#[doc = "Field `DCACHE_WRITE_FLASH` reader - The bit is used to indicate interrupt by dcache trying to write flash."]
+pub type DCACHE_WRITE_FLASH_R = crate::BitReader;
+#[doc = "Field `MMU_ENTRY_FAULT` reader - The bit is used to indicate interrupt by mmu entry fault."]
+pub type MMU_ENTRY_FAULT_R = crate::BitReader;
+#[doc = "Field `DCACHE_OCCUPY_EXC` reader - The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+pub type DCACHE_OCCUPY_EXC_R = crate::BitReader;
+#[doc = "Field `IBUS_ACS_CNT_OVF` reader - The bit is used to indicate interrupt by ibus access flash/spiram counter overflow."]
+pub type IBUS_ACS_CNT_OVF_R = crate::BitReader;
+#[doc = "Field `IBUS_ACS_MISS_CNT_OVF` reader - The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow."]
+pub type IBUS_ACS_MISS_CNT_OVF_R = crate::BitReader;
+#[doc = "Field `DBUS_ACS_CNT_OVF` reader - The bit is used to indicate interrupt by dbus access flash/spiram counter overflow."]
+pub type DBUS_ACS_CNT_OVF_R = crate::BitReader;
+#[doc = "Field `DBUS_ACS_FLASH_MISS_CNT_OVF` reader - The bit is used to indicate interrupt by dbus access flash miss counter overflow."]
+pub type DBUS_ACS_FLASH_MISS_CNT_OVF_R = crate::BitReader;
+#[doc = "Field `DBUS_ACS_SPIRAM_MISS_CNT_OVF` reader - The bit is used to indicate interrupt by dbus access spiram miss counter overflow."]
+pub type DBUS_ACS_SPIRAM_MISS_CNT_OVF_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to indicate interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn icache_sync_op_fault(&self) -> ICACHE_SYNC_OP_FAULT_R {
+        ICACHE_SYNC_OP_FAULT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn icache_preload_op_fault(&self) -> ICACHE_PRELOAD_OP_FAULT_R {
+        ICACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate interrupt by sync configurations fault."]
+    #[inline(always)]
+    pub fn dcache_sync_op_fault(&self) -> DCACHE_SYNC_OP_FAULT_R {
+        DCACHE_SYNC_OP_FAULT_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate interrupt by preload configurations fault."]
+    #[inline(always)]
+    pub fn dcache_preload_op_fault(&self) -> DCACHE_PRELOAD_OP_FAULT_R {
+        DCACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to indicate interrupt by dcache trying to write flash."]
+    #[inline(always)]
+    pub fn dcache_write_flash(&self) -> DCACHE_WRITE_FLASH_R {
+        DCACHE_WRITE_FLASH_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The bit is used to indicate interrupt by mmu entry fault."]
+    #[inline(always)]
+    pub fn mmu_entry_fault(&self) -> MMU_ENTRY_FAULT_R {
+        MMU_ENTRY_FAULT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
+    #[inline(always)]
+    pub fn dcache_occupy_exc(&self) -> DCACHE_OCCUPY_EXC_R {
+        DCACHE_OCCUPY_EXC_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The bit is used to indicate interrupt by ibus access flash/spiram counter overflow."]
+    #[inline(always)]
+    pub fn ibus_acs_cnt_ovf(&self) -> IBUS_ACS_CNT_OVF_R {
+        IBUS_ACS_CNT_OVF_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow."]
+    #[inline(always)]
+    pub fn ibus_acs_miss_cnt_ovf(&self) -> IBUS_ACS_MISS_CNT_OVF_R {
+        IBUS_ACS_MISS_CNT_OVF_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - The bit is used to indicate interrupt by dbus access flash/spiram counter overflow."]
+    #[inline(always)]
+    pub fn dbus_acs_cnt_ovf(&self) -> DBUS_ACS_CNT_OVF_R {
+        DBUS_ACS_CNT_OVF_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - The bit is used to indicate interrupt by dbus access flash miss counter overflow."]
+    #[inline(always)]
+    pub fn dbus_acs_flash_miss_cnt_ovf(&self) -> DBUS_ACS_FLASH_MISS_CNT_OVF_R {
+        DBUS_ACS_FLASH_MISS_CNT_OVF_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - The bit is used to indicate interrupt by dbus access spiram miss counter overflow."]
+    #[inline(always)]
+    pub fn dbus_acs_spiram_miss_cnt_ovf(&self) -> DBUS_ACS_SPIRAM_MISS_CNT_OVF_R {
+        DBUS_ACS_SPIRAM_MISS_CNT_OVF_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_ILG_INT_ST")
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("dcache_sync_op_fault", &self.dcache_sync_op_fault())
+            .field("dcache_preload_op_fault", &self.dcache_preload_op_fault())
+            .field("dcache_write_flash", &self.dcache_write_flash())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("dcache_occupy_exc", &self.dcache_occupy_exc())
+            .field("ibus_acs_cnt_ovf", &self.ibus_acs_cnt_ovf())
+            .field("ibus_acs_miss_cnt_ovf", &self.ibus_acs_miss_cnt_ovf())
+            .field("dbus_acs_cnt_ovf", &self.dbus_acs_cnt_ovf())
+            .field(
+                "dbus_acs_flash_miss_cnt_ovf",
+                &self.dbus_acs_flash_miss_cnt_ovf(),
+            )
+            .field(
+                "dbus_acs_spiram_miss_cnt_ovf",
+                &self.dbus_acs_spiram_miss_cnt_ovf(),
+            )
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_ILG_INT_ST_SPEC;
+impl crate::RegisterSpec for CACHE_ILG_INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_ilg_int_st::R`](R) reader structure"]
+impl crate::Readable for CACHE_ILG_INT_ST_SPEC {}
+#[doc = "`reset()` method sets CACHE_ILG_INT_ST to value 0"]
+impl crate::Resettable for CACHE_ILG_INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_mmu_fault_content.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `CACHE_MMU_FAULT_CONTENT` reader"]
+pub type R = crate::R<CACHE_MMU_FAULT_CONTENT_SPEC>;
+#[doc = "Field `CACHE_MMU_FAULT_CONTENT` reader - The bits are used to indicate the content of mmu entry which cause mmu fault.."]
+pub type CACHE_MMU_FAULT_CONTENT_R = crate::FieldReader<u16>;
+#[doc = "Field `CACHE_MMU_FAULT_CODE` reader - The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache."]
+pub type CACHE_MMU_FAULT_CODE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to indicate the content of mmu entry which cause mmu fault.."]
+    #[inline(always)]
+    pub fn cache_mmu_fault_content(&self) -> CACHE_MMU_FAULT_CONTENT_R {
+        CACHE_MMU_FAULT_CONTENT_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:19 - The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache."]
+    #[inline(always)]
+    pub fn cache_mmu_fault_code(&self) -> CACHE_MMU_FAULT_CODE_R {
+        CACHE_MMU_FAULT_CODE_R::new(((self.bits >> 16) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_MMU_FAULT_CONTENT")
+            .field("cache_mmu_fault_content", &self.cache_mmu_fault_content())
+            .field("cache_mmu_fault_code", &self.cache_mmu_fault_code())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_fault_content::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_MMU_FAULT_CONTENT_SPEC;
+impl crate::RegisterSpec for CACHE_MMU_FAULT_CONTENT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_mmu_fault_content::R`](R) reader structure"]
+impl crate::Readable for CACHE_MMU_FAULT_CONTENT_SPEC {}
+#[doc = "`reset()` method sets CACHE_MMU_FAULT_CONTENT to value 0"]
+impl crate::Resettable for CACHE_MMU_FAULT_CONTENT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_mmu_fault_vaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CACHE_MMU_FAULT_VADDR` reader"]
+pub type R = crate::R<CACHE_MMU_FAULT_VADDR_SPEC>;
+#[doc = "Field `CACHE_MMU_FAULT_VADDR` reader - The bits are used to indicate the virtual address which cause mmu fault.."]
+pub type CACHE_MMU_FAULT_VADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to indicate the virtual address which cause mmu fault.."]
+    #[inline(always)]
+    pub fn cache_mmu_fault_vaddr(&self) -> CACHE_MMU_FAULT_VADDR_R {
+        CACHE_MMU_FAULT_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_MMU_FAULT_VADDR")
+            .field("cache_mmu_fault_vaddr", &self.cache_mmu_fault_vaddr())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_fault_vaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_MMU_FAULT_VADDR_SPEC;
+impl crate::RegisterSpec for CACHE_MMU_FAULT_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_mmu_fault_vaddr::R`](R) reader structure"]
+impl crate::Readable for CACHE_MMU_FAULT_VADDR_SPEC {}
+#[doc = "`reset()` method sets CACHE_MMU_FAULT_VADDR to value 0"]
+impl crate::Resettable for CACHE_MMU_FAULT_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_mmu_owner.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CACHE_MMU_OWNER` reader"]
+pub type R = crate::R<CACHE_MMU_OWNER_SPEC>;
+#[doc = "Register `CACHE_MMU_OWNER` writer"]
+pub type W = crate::W<CACHE_MMU_OWNER_SPEC>;
+#[doc = "Field `CACHE_MMU_OWNER` reader - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
+pub type CACHE_MMU_OWNER_R = crate::FieldReader<u32>;
+#[doc = "Field `CACHE_MMU_OWNER` writer - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
+pub type CACHE_MMU_OWNER_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
+    #[inline(always)]
+    pub fn cache_mmu_owner(&self) -> CACHE_MMU_OWNER_R {
+        CACHE_MMU_OWNER_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_MMU_OWNER")
+            .field("cache_mmu_owner", &self.cache_mmu_owner())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
+    #[inline(always)]
+    pub fn cache_mmu_owner(&mut self) -> CACHE_MMU_OWNER_W<CACHE_MMU_OWNER_SPEC> {
+        CACHE_MMU_OWNER_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_owner::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_owner::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_MMU_OWNER_SPEC;
+impl crate::RegisterSpec for CACHE_MMU_OWNER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_mmu_owner::R`](R) reader structure"]
+impl crate::Readable for CACHE_MMU_OWNER_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_mmu_owner::W`](W) writer structure"]
+impl crate::Writable for CACHE_MMU_OWNER_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_MMU_OWNER to value 0"]
+impl crate::Resettable for CACHE_MMU_OWNER_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_mmu_power_ctrl.rs

@@ -0,0 +1,83 @@
+#[doc = "Register `CACHE_MMU_POWER_CTRL` reader"]
+pub type R = crate::R<CACHE_MMU_POWER_CTRL_SPEC>;
+#[doc = "Register `CACHE_MMU_POWER_CTRL` writer"]
+pub type W = crate::W<CACHE_MMU_POWER_CTRL_SPEC>;
+#[doc = "Field `CACHE_MMU_MEM_FORCE_ON` reader - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
+pub type CACHE_MMU_MEM_FORCE_ON_R = crate::BitReader;
+#[doc = "Field `CACHE_MMU_MEM_FORCE_ON` writer - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
+pub type CACHE_MMU_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CACHE_MMU_MEM_FORCE_PD` reader - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
+pub type CACHE_MMU_MEM_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `CACHE_MMU_MEM_FORCE_PD` writer - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
+pub type CACHE_MMU_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CACHE_MMU_MEM_FORCE_PU` reader - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
+pub type CACHE_MMU_MEM_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `CACHE_MMU_MEM_FORCE_PU` writer - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
+pub type CACHE_MMU_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn cache_mmu_mem_force_on(&self) -> CACHE_MMU_MEM_FORCE_ON_R {
+        CACHE_MMU_MEM_FORCE_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
+    #[inline(always)]
+    pub fn cache_mmu_mem_force_pd(&self) -> CACHE_MMU_MEM_FORCE_PD_R {
+        CACHE_MMU_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
+    #[inline(always)]
+    pub fn cache_mmu_mem_force_pu(&self) -> CACHE_MMU_MEM_FORCE_PU_R {
+        CACHE_MMU_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_MMU_POWER_CTRL")
+            .field("cache_mmu_mem_force_on", &self.cache_mmu_mem_force_on())
+            .field("cache_mmu_mem_force_pd", &self.cache_mmu_mem_force_pd())
+            .field("cache_mmu_mem_force_pu", &self.cache_mmu_mem_force_pu())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn cache_mmu_mem_force_on(
+        &mut self,
+    ) -> CACHE_MMU_MEM_FORCE_ON_W<CACHE_MMU_POWER_CTRL_SPEC> {
+        CACHE_MMU_MEM_FORCE_ON_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
+    #[inline(always)]
+    pub fn cache_mmu_mem_force_pd(
+        &mut self,
+    ) -> CACHE_MMU_MEM_FORCE_PD_W<CACHE_MMU_POWER_CTRL_SPEC> {
+        CACHE_MMU_MEM_FORCE_PD_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
+    #[inline(always)]
+    pub fn cache_mmu_mem_force_pu(
+        &mut self,
+    ) -> CACHE_MMU_MEM_FORCE_PU_W<CACHE_MMU_POWER_CTRL_SPEC> {
+        CACHE_MMU_MEM_FORCE_PU_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_power_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_power_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_MMU_POWER_CTRL_SPEC;
+impl crate::RegisterSpec for CACHE_MMU_POWER_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_mmu_power_ctrl::R`](R) reader structure"]
+impl crate::Readable for CACHE_MMU_POWER_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_mmu_power_ctrl::W`](W) writer structure"]
+impl crate::Writable for CACHE_MMU_POWER_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_MMU_POWER_CTRL to value 0x05"]
+impl crate::Resettable for CACHE_MMU_POWER_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x05;
+}

vendor/esp32s3/src/extmem/cache_preload_int_ctrl.rs

@@ -0,0 +1,96 @@
+#[doc = "Register `CACHE_PRELOAD_INT_CTRL` reader"]
+pub type R = crate::R<CACHE_PRELOAD_INT_CTRL_SPEC>;
+#[doc = "Register `CACHE_PRELOAD_INT_CTRL` writer"]
+pub type W = crate::W<CACHE_PRELOAD_INT_CTRL_SPEC>;
+#[doc = "Field `ST` reader - The bit is used to indicate the interrupt by icache pre-load done."]
+pub type ST_R = crate::BitReader;
+#[doc = "Field `ENA` reader - The bit is used to enable the interrupt by icache pre-load done."]
+pub type ENA_R = crate::BitReader;
+#[doc = "Field `ENA` writer - The bit is used to enable the interrupt by icache pre-load done."]
+pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLR` writer - The bit is used to clear the interrupt by icache pre-load done."]
+pub type CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DCACHE_PRELOAD_INT_ST` reader - The bit is used to indicate the interrupt by dcache pre-load done."]
+pub type DCACHE_PRELOAD_INT_ST_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_INT_ENA` reader - The bit is used to enable the interrupt by dcache pre-load done."]
+pub type DCACHE_PRELOAD_INT_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_INT_ENA` writer - The bit is used to enable the interrupt by dcache pre-load done."]
+pub type DCACHE_PRELOAD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_PRELOAD_INT_CLR` writer - The bit is used to clear the interrupt by dcache pre-load done."]
+pub type DCACHE_PRELOAD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to indicate the interrupt by icache pre-load done."]
+    #[inline(always)]
+    pub fn st(&self) -> ST_R {
+        ST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
+    #[inline(always)]
+    pub fn ena(&self) -> ENA_R {
+        ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate the interrupt by dcache pre-load done."]
+    #[inline(always)]
+    pub fn dcache_preload_int_st(&self) -> DCACHE_PRELOAD_INT_ST_R {
+        DCACHE_PRELOAD_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache pre-load done."]
+    #[inline(always)]
+    pub fn dcache_preload_int_ena(&self) -> DCACHE_PRELOAD_INT_ENA_R {
+        DCACHE_PRELOAD_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_PRELOAD_INT_CTRL")
+            .field("st", &self.st())
+            .field("ena", &self.ena())
+            .field("dcache_preload_int_st", &self.dcache_preload_int_st())
+            .field("dcache_preload_int_ena", &self.dcache_preload_int_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
+    #[inline(always)]
+    pub fn ena(&mut self) -> ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
+        ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to clear the interrupt by icache pre-load done."]
+    #[inline(always)]
+    pub fn clr(&mut self) -> CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
+        CLR_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache pre-load done."]
+    #[inline(always)]
+    pub fn dcache_preload_int_ena(
+        &mut self,
+    ) -> DCACHE_PRELOAD_INT_ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
+        DCACHE_PRELOAD_INT_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache pre-load done."]
+    #[inline(always)]
+    pub fn dcache_preload_int_clr(
+        &mut self,
+    ) -> DCACHE_PRELOAD_INT_CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
+        DCACHE_PRELOAD_INT_CLR_W::new(self, 5)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_preload_int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_preload_int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_PRELOAD_INT_CTRL_SPEC;
+impl crate::RegisterSpec for CACHE_PRELOAD_INT_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_preload_int_ctrl::R`](R) reader structure"]
+impl crate::Readable for CACHE_PRELOAD_INT_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_preload_int_ctrl::W`](W) writer structure"]
+impl crate::Writable for CACHE_PRELOAD_INT_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x04;
+}
+#[doc = "`reset()` method sets CACHE_PRELOAD_INT_CTRL to value 0"]
+impl crate::Resettable for CACHE_PRELOAD_INT_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_request.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CACHE_REQUEST` reader"]
+pub type R = crate::R<CACHE_REQUEST_SPEC>;
+#[doc = "Register `CACHE_REQUEST` writer"]
+pub type W = crate::W<CACHE_REQUEST_SPEC>;
+#[doc = "Field `BYPASS` reader - The bit is used to disable request recording which could cause performance issue"]
+pub type BYPASS_R = crate::BitReader;
+#[doc = "Field `BYPASS` writer - The bit is used to disable request recording which could cause performance issue"]
+pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
+    #[inline(always)]
+    pub fn bypass(&self) -> BYPASS_R {
+        BYPASS_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_REQUEST")
+            .field("bypass", &self.bypass())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
+    #[inline(always)]
+    pub fn bypass(&mut self) -> BYPASS_W<CACHE_REQUEST_SPEC> {
+        BYPASS_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_request::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_request::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_REQUEST_SPEC;
+impl crate::RegisterSpec for CACHE_REQUEST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_request::R`](R) reader structure"]
+impl crate::Readable for CACHE_REQUEST_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_request::W`](W) writer structure"]
+impl crate::Writable for CACHE_REQUEST_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_REQUEST to value 0"]
+impl crate::Resettable for CACHE_REQUEST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_state.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `CACHE_STATE` reader"]
+pub type R = crate::R<CACHE_STATE_SPEC>;
+#[doc = "Field `ICACHE_STATE` reader - The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state"]
+pub type ICACHE_STATE_R = crate::FieldReader<u16>;
+#[doc = "Field `DCACHE_STATE` reader - The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state"]
+pub type DCACHE_STATE_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:11 - The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state"]
+    #[inline(always)]
+    pub fn icache_state(&self) -> ICACHE_STATE_R {
+        ICACHE_STATE_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 12:23 - The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state"]
+    #[inline(always)]
+    pub fn dcache_state(&self) -> DCACHE_STATE_R {
+        DCACHE_STATE_R::new(((self.bits >> 12) & 0x0fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_STATE")
+            .field("icache_state", &self.icache_state())
+            .field("dcache_state", &self.dcache_state())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_STATE_SPEC;
+impl crate::RegisterSpec for CACHE_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_state::R`](R) reader structure"]
+impl crate::Readable for CACHE_STATE_SPEC {}
+#[doc = "`reset()` method sets CACHE_STATE to value 0"]
+impl crate::Resettable for CACHE_STATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_sync_int_ctrl.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `CACHE_SYNC_INT_CTRL` reader"]
+pub type R = crate::R<CACHE_SYNC_INT_CTRL_SPEC>;
+#[doc = "Register `CACHE_SYNC_INT_CTRL` writer"]
+pub type W = crate::W<CACHE_SYNC_INT_CTRL_SPEC>;
+#[doc = "Field `ST` reader - The bit is used to indicate the interrupt by icache sync done."]
+pub type ST_R = crate::BitReader;
+#[doc = "Field `ENA` reader - The bit is used to enable the interrupt by icache sync done."]
+pub type ENA_R = crate::BitReader;
+#[doc = "Field `ENA` writer - The bit is used to enable the interrupt by icache sync done."]
+pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLR` writer - The bit is used to clear the interrupt by icache sync done."]
+pub type CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DCACHE_SYNC_INT_ST` reader - The bit is used to indicate the interrupt by dcache sync done."]
+pub type DCACHE_SYNC_INT_ST_R = crate::BitReader;
+#[doc = "Field `DCACHE_SYNC_INT_ENA` reader - The bit is used to enable the interrupt by dcache sync done."]
+pub type DCACHE_SYNC_INT_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_SYNC_INT_ENA` writer - The bit is used to enable the interrupt by dcache sync done."]
+pub type DCACHE_SYNC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_SYNC_INT_CLR` writer - The bit is used to clear the interrupt by dcache sync done."]
+pub type DCACHE_SYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to indicate the interrupt by icache sync done."]
+    #[inline(always)]
+    pub fn st(&self) -> ST_R {
+        ST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
+    #[inline(always)]
+    pub fn ena(&self) -> ENA_R {
+        ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate the interrupt by dcache sync done."]
+    #[inline(always)]
+    pub fn dcache_sync_int_st(&self) -> DCACHE_SYNC_INT_ST_R {
+        DCACHE_SYNC_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache sync done."]
+    #[inline(always)]
+    pub fn dcache_sync_int_ena(&self) -> DCACHE_SYNC_INT_ENA_R {
+        DCACHE_SYNC_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_SYNC_INT_CTRL")
+            .field("st", &self.st())
+            .field("ena", &self.ena())
+            .field("dcache_sync_int_st", &self.dcache_sync_int_st())
+            .field("dcache_sync_int_ena", &self.dcache_sync_int_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
+    #[inline(always)]
+    pub fn ena(&mut self) -> ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
+        ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to clear the interrupt by icache sync done."]
+    #[inline(always)]
+    pub fn clr(&mut self) -> CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
+        CLR_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache sync done."]
+    #[inline(always)]
+    pub fn dcache_sync_int_ena(&mut self) -> DCACHE_SYNC_INT_ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
+        DCACHE_SYNC_INT_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache sync done."]
+    #[inline(always)]
+    pub fn dcache_sync_int_clr(&mut self) -> DCACHE_SYNC_INT_CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
+        DCACHE_SYNC_INT_CLR_W::new(self, 5)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sync_int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sync_int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_SYNC_INT_CTRL_SPEC;
+impl crate::RegisterSpec for CACHE_SYNC_INT_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_sync_int_ctrl::R`](R) reader structure"]
+impl crate::Readable for CACHE_SYNC_INT_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_sync_int_ctrl::W`](W) writer structure"]
+impl crate::Writable for CACHE_SYNC_INT_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x04;
+}
+#[doc = "`reset()` method sets CACHE_SYNC_INT_CTRL to value 0"]
+impl crate::Resettable for CACHE_SYNC_INT_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_tag_content.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CACHE_TAG_CONTENT` reader"]
+pub type R = crate::R<CACHE_TAG_CONTENT_SPEC>;
+#[doc = "Register `CACHE_TAG_CONTENT` writer"]
+pub type W = crate::W<CACHE_TAG_CONTENT_SPEC>;
+#[doc = "Field `CACHE_TAG_CONTENT` reader - This is a constant place where we can write data to or read data from the tag memory on the specified cache."]
+pub type CACHE_TAG_CONTENT_R = crate::FieldReader<u32>;
+#[doc = "Field `CACHE_TAG_CONTENT` writer - This is a constant place where we can write data to or read data from the tag memory on the specified cache."]
+pub type CACHE_TAG_CONTENT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag memory on the specified cache."]
+    #[inline(always)]
+    pub fn cache_tag_content(&self) -> CACHE_TAG_CONTENT_R {
+        CACHE_TAG_CONTENT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_TAG_CONTENT")
+            .field("cache_tag_content", &self.cache_tag_content())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag memory on the specified cache."]
+    #[inline(always)]
+    pub fn cache_tag_content(&mut self) -> CACHE_TAG_CONTENT_W<CACHE_TAG_CONTENT_SPEC> {
+        CACHE_TAG_CONTENT_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_content::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_content::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_TAG_CONTENT_SPEC;
+impl crate::RegisterSpec for CACHE_TAG_CONTENT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_tag_content::R`](R) reader structure"]
+impl crate::Readable for CACHE_TAG_CONTENT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_tag_content::W`](W) writer structure"]
+impl crate::Writable for CACHE_TAG_CONTENT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_TAG_CONTENT to value 0"]
+impl crate::Resettable for CACHE_TAG_CONTENT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_tag_object_ctrl.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CACHE_TAG_OBJECT_CTRL` reader"]
+pub type R = crate::R<CACHE_TAG_OBJECT_CTRL_SPEC>;
+#[doc = "Register `CACHE_TAG_OBJECT_CTRL` writer"]
+pub type W = crate::W<CACHE_TAG_OBJECT_CTRL_SPEC>;
+#[doc = "Field `ICACHE_TAG_OBJECT` reader - Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register."]
+pub type ICACHE_TAG_OBJECT_R = crate::BitReader;
+#[doc = "Field `ICACHE_TAG_OBJECT` writer - Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register."]
+pub type ICACHE_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_TAG_OBJECT` reader - Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register."]
+pub type DCACHE_TAG_OBJECT_R = crate::BitReader;
+#[doc = "Field `DCACHE_TAG_OBJECT` writer - Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register."]
+pub type DCACHE_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register."]
+    #[inline(always)]
+    pub fn icache_tag_object(&self) -> ICACHE_TAG_OBJECT_R {
+        ICACHE_TAG_OBJECT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register."]
+    #[inline(always)]
+    pub fn dcache_tag_object(&self) -> DCACHE_TAG_OBJECT_R {
+        DCACHE_TAG_OBJECT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_TAG_OBJECT_CTRL")
+            .field("icache_tag_object", &self.icache_tag_object())
+            .field("dcache_tag_object", &self.dcache_tag_object())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register."]
+    #[inline(always)]
+    pub fn icache_tag_object(&mut self) -> ICACHE_TAG_OBJECT_W<CACHE_TAG_OBJECT_CTRL_SPEC> {
+        ICACHE_TAG_OBJECT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register."]
+    #[inline(always)]
+    pub fn dcache_tag_object(&mut self) -> DCACHE_TAG_OBJECT_W<CACHE_TAG_OBJECT_CTRL_SPEC> {
+        DCACHE_TAG_OBJECT_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_object_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_object_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_TAG_OBJECT_CTRL_SPEC;
+impl crate::RegisterSpec for CACHE_TAG_OBJECT_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_tag_object_ctrl::R`](R) reader structure"]
+impl crate::Readable for CACHE_TAG_OBJECT_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_tag_object_ctrl::W`](W) writer structure"]
+impl crate::Writable for CACHE_TAG_OBJECT_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_TAG_OBJECT_CTRL to value 0"]
+impl crate::Resettable for CACHE_TAG_OBJECT_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_tag_way_object.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CACHE_TAG_WAY_OBJECT` reader"]
+pub type R = crate::R<CACHE_TAG_WAY_OBJECT_SPEC>;
+#[doc = "Register `CACHE_TAG_WAY_OBJECT` writer"]
+pub type W = crate::W<CACHE_TAG_WAY_OBJECT_SPEC>;
+#[doc = "Field `CACHE_TAG_WAY_OBJECT` reader - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7."]
+pub type CACHE_TAG_WAY_OBJECT_R = crate::FieldReader;
+#[doc = "Field `CACHE_TAG_WAY_OBJECT` writer - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7."]
+pub type CACHE_TAG_WAY_OBJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7."]
+    #[inline(always)]
+    pub fn cache_tag_way_object(&self) -> CACHE_TAG_WAY_OBJECT_R {
+        CACHE_TAG_WAY_OBJECT_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_TAG_WAY_OBJECT")
+            .field("cache_tag_way_object", &self.cache_tag_way_object())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7."]
+    #[inline(always)]
+    pub fn cache_tag_way_object(&mut self) -> CACHE_TAG_WAY_OBJECT_W<CACHE_TAG_WAY_OBJECT_SPEC> {
+        CACHE_TAG_WAY_OBJECT_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_way_object::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_way_object::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_TAG_WAY_OBJECT_SPEC;
+impl crate::RegisterSpec for CACHE_TAG_WAY_OBJECT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_tag_way_object::R`](R) reader structure"]
+impl crate::Readable for CACHE_TAG_WAY_OBJECT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_tag_way_object::W`](W) writer structure"]
+impl crate::Writable for CACHE_TAG_WAY_OBJECT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_TAG_WAY_OBJECT to value 0"]
+impl crate::Resettable for CACHE_TAG_WAY_OBJECT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_vaddr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CACHE_VADDR` reader"]
+pub type R = crate::R<CACHE_VADDR_SPEC>;
+#[doc = "Register `CACHE_VADDR` writer"]
+pub type W = crate::W<CACHE_VADDR_SPEC>;
+#[doc = "Field `CACHE_VADDR` reader - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
+pub type CACHE_VADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `CACHE_VADDR` writer - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
+pub type CACHE_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
+    #[inline(always)]
+    pub fn cache_vaddr(&self) -> CACHE_VADDR_R {
+        CACHE_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_VADDR")
+            .field("cache_vaddr", &self.cache_vaddr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
+    #[inline(always)]
+    pub fn cache_vaddr(&mut self) -> CACHE_VADDR_W<CACHE_VADDR_SPEC> {
+        CACHE_VADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_vaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_vaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_VADDR_SPEC;
+impl crate::RegisterSpec for CACHE_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_vaddr::R`](R) reader structure"]
+impl crate::Readable for CACHE_VADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_vaddr::W`](W) writer structure"]
+impl crate::Writable for CACHE_VADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_VADDR to value 0"]
+impl crate::Resettable for CACHE_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/cache_wrap_around_ctrl.rs

@@ -0,0 +1,69 @@
+#[doc = "Register `CACHE_WRAP_AROUND_CTRL` reader"]
+pub type R = crate::R<CACHE_WRAP_AROUND_CTRL_SPEC>;
+#[doc = "Register `CACHE_WRAP_AROUND_CTRL` writer"]
+pub type W = crate::W<CACHE_WRAP_AROUND_CTRL_SPEC>;
+#[doc = "Field `CACHE_FLASH_WRAP_AROUND` reader - The bit is used to enable wrap around mode when read data from flash."]
+pub type CACHE_FLASH_WRAP_AROUND_R = crate::BitReader;
+#[doc = "Field `CACHE_FLASH_WRAP_AROUND` writer - The bit is used to enable wrap around mode when read data from flash."]
+pub type CACHE_FLASH_WRAP_AROUND_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CACHE_SRAM_RD_WRAP_AROUND` reader - The bit is used to enable wrap around mode when read data from spiram."]
+pub type CACHE_SRAM_RD_WRAP_AROUND_R = crate::BitReader;
+#[doc = "Field `CACHE_SRAM_RD_WRAP_AROUND` writer - The bit is used to enable wrap around mode when read data from spiram."]
+pub type CACHE_SRAM_RD_WRAP_AROUND_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
+    #[inline(always)]
+    pub fn cache_flash_wrap_around(&self) -> CACHE_FLASH_WRAP_AROUND_R {
+        CACHE_FLASH_WRAP_AROUND_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable wrap around mode when read data from spiram."]
+    #[inline(always)]
+    pub fn cache_sram_rd_wrap_around(&self) -> CACHE_SRAM_RD_WRAP_AROUND_R {
+        CACHE_SRAM_RD_WRAP_AROUND_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_WRAP_AROUND_CTRL")
+            .field("cache_flash_wrap_around", &self.cache_flash_wrap_around())
+            .field(
+                "cache_sram_rd_wrap_around",
+                &self.cache_sram_rd_wrap_around(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
+    #[inline(always)]
+    pub fn cache_flash_wrap_around(
+        &mut self,
+    ) -> CACHE_FLASH_WRAP_AROUND_W<CACHE_WRAP_AROUND_CTRL_SPEC> {
+        CACHE_FLASH_WRAP_AROUND_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable wrap around mode when read data from spiram."]
+    #[inline(always)]
+    pub fn cache_sram_rd_wrap_around(
+        &mut self,
+    ) -> CACHE_SRAM_RD_WRAP_AROUND_W<CACHE_WRAP_AROUND_CTRL_SPEC> {
+        CACHE_SRAM_RD_WRAP_AROUND_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_wrap_around_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_wrap_around_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_WRAP_AROUND_CTRL_SPEC;
+impl crate::RegisterSpec for CACHE_WRAP_AROUND_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_wrap_around_ctrl::R`](R) reader structure"]
+impl crate::Readable for CACHE_WRAP_AROUND_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_wrap_around_ctrl::W`](W) writer structure"]
+impl crate::Writable for CACHE_WRAP_AROUND_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CACHE_WRAP_AROUND_CTRL to value 0"]
+impl crate::Resettable for CACHE_WRAP_AROUND_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/clock_gate.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CLOCK_GATE` reader"]
+pub type R = crate::R<CLOCK_GATE_SPEC>;
+#[doc = "Register `CLOCK_GATE` writer"]
+pub type W = crate::W<CLOCK_GATE_SPEC>;
+#[doc = "Field `CLK_EN` reader - Reserved"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - Reserved"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Reserved"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLOCK_GATE")
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Reserved"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
+        CLK_EN_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLOCK_GATE_SPEC;
+impl crate::RegisterSpec for CLOCK_GATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
+impl crate::Readable for CLOCK_GATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
+impl crate::Writable for CLOCK_GATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"]
+impl crate::Resettable for CLOCK_GATE_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/extmem/core0_acs_cache_int_clr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `CORE0_ACS_CACHE_INT_CLR` writer"]
+pub type W = crate::W<CORE0_ACS_CACHE_INT_CLR_SPEC>;
+#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` writer - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
+pub type CORE0_IBUS_ACS_MSK_IC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CORE0_IBUS_WR_IC` writer - The bit is used to clear interrupt by ibus trying to write icache"]
+pub type CORE0_IBUS_WR_IC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CORE0_IBUS_REJECT` writer - The bit is used to clear interrupt by authentication fail."]
+pub type CORE0_IBUS_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CORE0_DBUS_ACS_MSK_DC` writer - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
+pub type CORE0_DBUS_ACS_MSK_DC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CORE0_DBUS_REJECT` writer - The bit is used to clear interrupt by authentication fail."]
+pub type CORE0_DBUS_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_ibus_acs_msk_ic(
+        &mut self,
+    ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
+        CORE0_IBUS_ACS_MSK_IC_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to clear interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
+        CORE0_IBUS_WR_IC_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to clear interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
+        CORE0_IBUS_REJECT_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_dbus_acs_msk_dc(
+        &mut self,
+    ) -> CORE0_DBUS_ACS_MSK_DC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
+        CORE0_DBUS_ACS_MSK_DC_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The bit is used to clear interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
+        CORE0_DBUS_REJECT_W::new(self, 4)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_ACS_CACHE_INT_CLR_SPEC;
+impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`core0_acs_cache_int_clr::W`](W) writer structure"]
+impl crate::Writable for CORE0_ACS_CACHE_INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1f;
+}
+#[doc = "`reset()` method sets CORE0_ACS_CACHE_INT_CLR to value 0"]
+impl crate::Resettable for CORE0_ACS_CACHE_INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core0_acs_cache_int_ena.rs

@@ -0,0 +1,111 @@
+#[doc = "Register `CORE0_ACS_CACHE_INT_ENA` reader"]
+pub type R = crate::R<CORE0_ACS_CACHE_INT_ENA_SPEC>;
+#[doc = "Register `CORE0_ACS_CACHE_INT_ENA` writer"]
+pub type W = crate::W<CORE0_ACS_CACHE_INT_ENA_SPEC>;
+#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` reader - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+pub type CORE0_IBUS_ACS_MSK_IC_R = crate::BitReader;
+#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` writer - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+pub type CORE0_IBUS_ACS_MSK_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE0_IBUS_WR_IC` reader - The bit is used to enable interrupt by ibus trying to write icache"]
+pub type CORE0_IBUS_WR_IC_R = crate::BitReader;
+#[doc = "Field `CORE0_IBUS_WR_IC` writer - The bit is used to enable interrupt by ibus trying to write icache"]
+pub type CORE0_IBUS_WR_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE0_IBUS_REJECT` reader - The bit is used to enable interrupt by authentication fail."]
+pub type CORE0_IBUS_REJECT_R = crate::BitReader;
+#[doc = "Field `CORE0_IBUS_REJECT` writer - The bit is used to enable interrupt by authentication fail."]
+pub type CORE0_IBUS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE0_DBUS_ACS_MSK_DC` reader - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+pub type CORE0_DBUS_ACS_MSK_DC_R = crate::BitReader;
+#[doc = "Field `CORE0_DBUS_ACS_MSK_DC` writer - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+pub type CORE0_DBUS_ACS_MSK_DC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE0_DBUS_REJECT` reader - The bit is used to enable interrupt by authentication fail."]
+pub type CORE0_DBUS_REJECT_R = crate::BitReader;
+#[doc = "Field `CORE0_DBUS_REJECT` writer - The bit is used to enable interrupt by authentication fail."]
+pub type CORE0_DBUS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_ibus_acs_msk_ic(&self) -> CORE0_IBUS_ACS_MSK_IC_R {
+        CORE0_IBUS_ACS_MSK_IC_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core0_ibus_wr_ic(&self) -> CORE0_IBUS_WR_IC_R {
+        CORE0_IBUS_WR_IC_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_ibus_reject(&self) -> CORE0_IBUS_REJECT_R {
+        CORE0_IBUS_REJECT_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_dbus_acs_msk_dc(&self) -> CORE0_DBUS_ACS_MSK_DC_R {
+        CORE0_DBUS_ACS_MSK_DC_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_dbus_reject(&self) -> CORE0_DBUS_REJECT_R {
+        CORE0_DBUS_REJECT_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE0_ACS_CACHE_INT_ENA")
+            .field("core0_ibus_acs_msk_ic", &self.core0_ibus_acs_msk_ic())
+            .field("core0_ibus_wr_ic", &self.core0_ibus_wr_ic())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
+            .field("core0_dbus_acs_msk_dc", &self.core0_dbus_acs_msk_dc())
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_ibus_acs_msk_ic(
+        &mut self,
+    ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
+        CORE0_IBUS_ACS_MSK_IC_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
+        CORE0_IBUS_WR_IC_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
+        CORE0_IBUS_REJECT_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_dbus_acs_msk_dc(
+        &mut self,
+    ) -> CORE0_DBUS_ACS_MSK_DC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
+        CORE0_DBUS_ACS_MSK_DC_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
+        CORE0_DBUS_REJECT_W::new(self, 4)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_acs_cache_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_ACS_CACHE_INT_ENA_SPEC;
+impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core0_acs_cache_int_ena::R`](R) reader structure"]
+impl crate::Readable for CORE0_ACS_CACHE_INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core0_acs_cache_int_ena::W`](W) writer structure"]
+impl crate::Writable for CORE0_ACS_CACHE_INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE0_ACS_CACHE_INT_ENA to value 0"]
+impl crate::Resettable for CORE0_ACS_CACHE_INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core0_acs_cache_int_st.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `CORE0_ACS_CACHE_INT_ST` reader"]
+pub type R = crate::R<CORE0_ACS_CACHE_INT_ST_SPEC>;
+#[doc = "Field `CORE0_IBUS_ACS_MSK_ICACHE` reader - The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access."]
+pub type CORE0_IBUS_ACS_MSK_ICACHE_R = crate::BitReader;
+#[doc = "Field `CORE0_IBUS_WR_ICACHE` reader - The bit is used to indicate interrupt by ibus trying to write icache"]
+pub type CORE0_IBUS_WR_ICACHE_R = crate::BitReader;
+#[doc = "Field `CORE0_IBUS_REJECT` reader - The bit is used to indicate interrupt by authentication fail."]
+pub type CORE0_IBUS_REJECT_R = crate::BitReader;
+#[doc = "Field `CORE0_DBUS_ACS_MSK_DCACHE` reader - The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access."]
+pub type CORE0_DBUS_ACS_MSK_DCACHE_R = crate::BitReader;
+#[doc = "Field `CORE0_DBUS_REJECT` reader - The bit is used to indicate interrupt by authentication fail."]
+pub type CORE0_DBUS_REJECT_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_ibus_acs_msk_icache(&self) -> CORE0_IBUS_ACS_MSK_ICACHE_R {
+        CORE0_IBUS_ACS_MSK_ICACHE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core0_ibus_wr_icache(&self) -> CORE0_IBUS_WR_ICACHE_R {
+        CORE0_IBUS_WR_ICACHE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_ibus_reject(&self) -> CORE0_IBUS_REJECT_R {
+        CORE0_IBUS_REJECT_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core0_dbus_acs_msk_dcache(&self) -> CORE0_DBUS_ACS_MSK_DCACHE_R {
+        CORE0_DBUS_ACS_MSK_DCACHE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to indicate interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core0_dbus_reject(&self) -> CORE0_DBUS_REJECT_R {
+        CORE0_DBUS_REJECT_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE0_ACS_CACHE_INT_ST")
+            .field(
+                "core0_ibus_acs_msk_icache",
+                &self.core0_ibus_acs_msk_icache(),
+            )
+            .field("core0_ibus_wr_icache", &self.core0_ibus_wr_icache())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
+            .field(
+                "core0_dbus_acs_msk_dcache",
+                &self.core0_dbus_acs_msk_dcache(),
+            )
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_acs_cache_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_ACS_CACHE_INT_ST_SPEC;
+impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core0_acs_cache_int_st::R`](R) reader structure"]
+impl crate::Readable for CORE0_ACS_CACHE_INT_ST_SPEC {}
+#[doc = "`reset()` method sets CORE0_ACS_CACHE_INT_ST to value 0"]
+impl crate::Resettable for CORE0_ACS_CACHE_INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core0_dbus_reject_st.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `CORE0_DBUS_REJECT_ST` reader"]
+pub type R = crate::R<CORE0_DBUS_REJECT_ST_SPEC>;
+#[doc = "Field `CORE0_DBUS_TAG_ATTR` reader - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+pub type CORE0_DBUS_TAG_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE0_DBUS_ATTR` reader - The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+pub type CORE0_DBUS_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE0_DBUS_WORLD` reader - The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1"]
+pub type CORE0_DBUS_WORLD_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:2 - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+    #[inline(always)]
+    pub fn core0_dbus_tag_attr(&self) -> CORE0_DBUS_TAG_ATTR_R {
+        CORE0_DBUS_TAG_ATTR_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+    #[inline(always)]
+    pub fn core0_dbus_attr(&self) -> CORE0_DBUS_ATTR_R {
+        CORE0_DBUS_ATTR_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1"]
+    #[inline(always)]
+    pub fn core0_dbus_world(&self) -> CORE0_DBUS_WORLD_R {
+        CORE0_DBUS_WORLD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE0_DBUS_REJECT_ST")
+            .field("core0_dbus_tag_attr", &self.core0_dbus_tag_attr())
+            .field("core0_dbus_attr", &self.core0_dbus_attr())
+            .field("core0_dbus_world", &self.core0_dbus_world())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_dbus_reject_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_DBUS_REJECT_ST_SPEC;
+impl crate::RegisterSpec for CORE0_DBUS_REJECT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core0_dbus_reject_st::R`](R) reader structure"]
+impl crate::Readable for CORE0_DBUS_REJECT_ST_SPEC {}
+#[doc = "`reset()` method sets CORE0_DBUS_REJECT_ST to value 0"]
+impl crate::Resettable for CORE0_DBUS_REJECT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core0_dbus_reject_vaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE0_DBUS_REJECT_VADDR` reader"]
+pub type R = crate::R<CORE0_DBUS_REJECT_VADDR_SPEC>;
+#[doc = "Field `CORE0_DBUS_VADDR` reader - The bits are used to indicate the virtual address of CPU access dbus when authentication fail."]
+pub type CORE0_DBUS_VADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to indicate the virtual address of CPU access dbus when authentication fail."]
+    #[inline(always)]
+    pub fn core0_dbus_vaddr(&self) -> CORE0_DBUS_VADDR_R {
+        CORE0_DBUS_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE0_DBUS_REJECT_VADDR")
+            .field("core0_dbus_vaddr", &self.core0_dbus_vaddr())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_dbus_reject_vaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_DBUS_REJECT_VADDR_SPEC;
+impl crate::RegisterSpec for CORE0_DBUS_REJECT_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core0_dbus_reject_vaddr::R`](R) reader structure"]
+impl crate::Readable for CORE0_DBUS_REJECT_VADDR_SPEC {}
+#[doc = "`reset()` method sets CORE0_DBUS_REJECT_VADDR to value 0xffff_ffff"]
+impl crate::Resettable for CORE0_DBUS_REJECT_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/extmem/core0_ibus_reject_st.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `CORE0_IBUS_REJECT_ST` reader"]
+pub type R = crate::R<CORE0_IBUS_REJECT_ST_SPEC>;
+#[doc = "Field `CORE0_IBUS_TAG_ATTR` reader - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+pub type CORE0_IBUS_TAG_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE0_IBUS_ATTR` reader - The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able"]
+pub type CORE0_IBUS_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE0_IBUS_WORLD` reader - The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1"]
+pub type CORE0_IBUS_WORLD_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:2 - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+    #[inline(always)]
+    pub fn core0_ibus_tag_attr(&self) -> CORE0_IBUS_TAG_ATTR_R {
+        CORE0_IBUS_TAG_ATTR_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able"]
+    #[inline(always)]
+    pub fn core0_ibus_attr(&self) -> CORE0_IBUS_ATTR_R {
+        CORE0_IBUS_ATTR_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1"]
+    #[inline(always)]
+    pub fn core0_ibus_world(&self) -> CORE0_IBUS_WORLD_R {
+        CORE0_IBUS_WORLD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE0_IBUS_REJECT_ST")
+            .field("core0_ibus_tag_attr", &self.core0_ibus_tag_attr())
+            .field("core0_ibus_attr", &self.core0_ibus_attr())
+            .field("core0_ibus_world", &self.core0_ibus_world())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_ibus_reject_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_IBUS_REJECT_ST_SPEC;
+impl crate::RegisterSpec for CORE0_IBUS_REJECT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core0_ibus_reject_st::R`](R) reader structure"]
+impl crate::Readable for CORE0_IBUS_REJECT_ST_SPEC {}
+#[doc = "`reset()` method sets CORE0_IBUS_REJECT_ST to value 0"]
+impl crate::Resettable for CORE0_IBUS_REJECT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core0_ibus_reject_vaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE0_IBUS_REJECT_VADDR` reader"]
+pub type R = crate::R<CORE0_IBUS_REJECT_VADDR_SPEC>;
+#[doc = "Field `CORE0_IBUS_VADDR` reader - The bits are used to indicate the virtual address of CPU access ibus when authentication fail."]
+pub type CORE0_IBUS_VADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to indicate the virtual address of CPU access ibus when authentication fail."]
+    #[inline(always)]
+    pub fn core0_ibus_vaddr(&self) -> CORE0_IBUS_VADDR_R {
+        CORE0_IBUS_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE0_IBUS_REJECT_VADDR")
+            .field("core0_ibus_vaddr", &self.core0_ibus_vaddr())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_ibus_reject_vaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE0_IBUS_REJECT_VADDR_SPEC;
+impl crate::RegisterSpec for CORE0_IBUS_REJECT_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core0_ibus_reject_vaddr::R`](R) reader structure"]
+impl crate::Readable for CORE0_IBUS_REJECT_VADDR_SPEC {}
+#[doc = "`reset()` method sets CORE0_IBUS_REJECT_VADDR to value 0xffff_ffff"]
+impl crate::Resettable for CORE0_IBUS_REJECT_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/extmem/core1_acs_cache_int_clr.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CORE1_ACS_CACHE_INT_CLR` writer"]
+pub type W = crate::W<CORE1_ACS_CACHE_INT_CLR_SPEC>;
+#[doc = "Field `CORE1_IBUS_ACS_MSK_IC_INT_CLR` writer - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
+pub type CORE1_IBUS_ACS_MSK_IC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_IBUS_WR_IC_INT_CLR` writer - The bit is used to clear interrupt by ibus trying to write icache"]
+pub type CORE1_IBUS_WR_IC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_IBUS_REJECT_INT_CLR` writer - The bit is used to clear interrupt by authentication fail."]
+pub type CORE1_IBUS_REJECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_DBUS_ACS_MSK_DC_INT_CLR` writer - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
+pub type CORE1_DBUS_ACS_MSK_DC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_DBUS_REJECT_INT_CLR` writer - The bit is used to clear interrupt by authentication fail."]
+pub type CORE1_DBUS_REJECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CORE1_ACS_CACHE_INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_ibus_acs_msk_ic_int_clr(
+        &mut self,
+    ) -> CORE1_IBUS_ACS_MSK_IC_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
+        CORE1_IBUS_ACS_MSK_IC_INT_CLR_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to clear interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core1_ibus_wr_ic_int_clr(
+        &mut self,
+    ) -> CORE1_IBUS_WR_IC_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
+        CORE1_IBUS_WR_IC_INT_CLR_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to clear interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_ibus_reject_int_clr(
+        &mut self,
+    ) -> CORE1_IBUS_REJECT_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
+        CORE1_IBUS_REJECT_INT_CLR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_dbus_acs_msk_dc_int_clr(
+        &mut self,
+    ) -> CORE1_DBUS_ACS_MSK_DC_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
+        CORE1_DBUS_ACS_MSK_DC_INT_CLR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The bit is used to clear interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_dbus_reject_int_clr(
+        &mut self,
+    ) -> CORE1_DBUS_REJECT_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
+        CORE1_DBUS_REJECT_INT_CLR_W::new(self, 4)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core1_acs_cache_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_ACS_CACHE_INT_CLR_SPEC;
+impl crate::RegisterSpec for CORE1_ACS_CACHE_INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`core1_acs_cache_int_clr::W`](W) writer structure"]
+impl crate::Writable for CORE1_ACS_CACHE_INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE1_ACS_CACHE_INT_CLR to value 0"]
+impl crate::Resettable for CORE1_ACS_CACHE_INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core1_acs_cache_int_ena.rs

@@ -0,0 +1,129 @@
+#[doc = "Register `CORE1_ACS_CACHE_INT_ENA` reader"]
+pub type R = crate::R<CORE1_ACS_CACHE_INT_ENA_SPEC>;
+#[doc = "Register `CORE1_ACS_CACHE_INT_ENA` writer"]
+pub type W = crate::W<CORE1_ACS_CACHE_INT_ENA_SPEC>;
+#[doc = "Field `CORE1_IBUS_ACS_MSK_IC_INT_ENA` reader - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+pub type CORE1_IBUS_ACS_MSK_IC_INT_ENA_R = crate::BitReader;
+#[doc = "Field `CORE1_IBUS_ACS_MSK_IC_INT_ENA` writer - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+pub type CORE1_IBUS_ACS_MSK_IC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_IBUS_WR_IC_INT_ENA` reader - The bit is used to enable interrupt by ibus trying to write icache"]
+pub type CORE1_IBUS_WR_IC_INT_ENA_R = crate::BitReader;
+#[doc = "Field `CORE1_IBUS_WR_IC_INT_ENA` writer - The bit is used to enable interrupt by ibus trying to write icache"]
+pub type CORE1_IBUS_WR_IC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_IBUS_REJECT_INT_ENA` reader - The bit is used to enable interrupt by authentication fail."]
+pub type CORE1_IBUS_REJECT_INT_ENA_R = crate::BitReader;
+#[doc = "Field `CORE1_IBUS_REJECT_INT_ENA` writer - The bit is used to enable interrupt by authentication fail."]
+pub type CORE1_IBUS_REJECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_DBUS_ACS_MSK_DC_INT_ENA` reader - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+pub type CORE1_DBUS_ACS_MSK_DC_INT_ENA_R = crate::BitReader;
+#[doc = "Field `CORE1_DBUS_ACS_MSK_DC_INT_ENA` writer - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+pub type CORE1_DBUS_ACS_MSK_DC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE1_DBUS_REJECT_INT_ENA` reader - The bit is used to enable interrupt by authentication fail."]
+pub type CORE1_DBUS_REJECT_INT_ENA_R = crate::BitReader;
+#[doc = "Field `CORE1_DBUS_REJECT_INT_ENA` writer - The bit is used to enable interrupt by authentication fail."]
+pub type CORE1_DBUS_REJECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_ibus_acs_msk_ic_int_ena(&self) -> CORE1_IBUS_ACS_MSK_IC_INT_ENA_R {
+        CORE1_IBUS_ACS_MSK_IC_INT_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core1_ibus_wr_ic_int_ena(&self) -> CORE1_IBUS_WR_IC_INT_ENA_R {
+        CORE1_IBUS_WR_IC_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_ibus_reject_int_ena(&self) -> CORE1_IBUS_REJECT_INT_ENA_R {
+        CORE1_IBUS_REJECT_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_dbus_acs_msk_dc_int_ena(&self) -> CORE1_DBUS_ACS_MSK_DC_INT_ENA_R {
+        CORE1_DBUS_ACS_MSK_DC_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_dbus_reject_int_ena(&self) -> CORE1_DBUS_REJECT_INT_ENA_R {
+        CORE1_DBUS_REJECT_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE1_ACS_CACHE_INT_ENA")
+            .field(
+                "core1_ibus_acs_msk_ic_int_ena",
+                &self.core1_ibus_acs_msk_ic_int_ena(),
+            )
+            .field("core1_ibus_wr_ic_int_ena", &self.core1_ibus_wr_ic_int_ena())
+            .field(
+                "core1_ibus_reject_int_ena",
+                &self.core1_ibus_reject_int_ena(),
+            )
+            .field(
+                "core1_dbus_acs_msk_dc_int_ena",
+                &self.core1_dbus_acs_msk_dc_int_ena(),
+            )
+            .field(
+                "core1_dbus_reject_int_ena",
+                &self.core1_dbus_reject_int_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_ibus_acs_msk_ic_int_ena(
+        &mut self,
+    ) -> CORE1_IBUS_ACS_MSK_IC_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
+        CORE1_IBUS_ACS_MSK_IC_INT_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core1_ibus_wr_ic_int_ena(
+        &mut self,
+    ) -> CORE1_IBUS_WR_IC_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
+        CORE1_IBUS_WR_IC_INT_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_ibus_reject_int_ena(
+        &mut self,
+    ) -> CORE1_IBUS_REJECT_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
+        CORE1_IBUS_REJECT_INT_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_dbus_acs_msk_dc_int_ena(
+        &mut self,
+    ) -> CORE1_DBUS_ACS_MSK_DC_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
+        CORE1_DBUS_ACS_MSK_DC_INT_ENA_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_dbus_reject_int_ena(
+        &mut self,
+    ) -> CORE1_DBUS_REJECT_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
+        CORE1_DBUS_REJECT_INT_ENA_W::new(self, 4)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_acs_cache_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core1_acs_cache_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_ACS_CACHE_INT_ENA_SPEC;
+impl crate::RegisterSpec for CORE1_ACS_CACHE_INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core1_acs_cache_int_ena::R`](R) reader structure"]
+impl crate::Readable for CORE1_ACS_CACHE_INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core1_acs_cache_int_ena::W`](W) writer structure"]
+impl crate::Writable for CORE1_ACS_CACHE_INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE1_ACS_CACHE_INT_ENA to value 0"]
+impl crate::Resettable for CORE1_ACS_CACHE_INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core1_acs_cache_int_st.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `CORE1_ACS_CACHE_INT_ST` reader"]
+pub type R = crate::R<CORE1_ACS_CACHE_INT_ST_SPEC>;
+#[doc = "Field `CORE1_IBUS_ACS_MSK_ICACHE_ST` reader - The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access."]
+pub type CORE1_IBUS_ACS_MSK_ICACHE_ST_R = crate::BitReader;
+#[doc = "Field `CORE1_IBUS_WR_ICACHE_ST` reader - The bit is used to indicate interrupt by ibus trying to write icache"]
+pub type CORE1_IBUS_WR_ICACHE_ST_R = crate::BitReader;
+#[doc = "Field `CORE1_IBUS_REJECT_ST` reader - The bit is used to indicate interrupt by authentication fail."]
+pub type CORE1_IBUS_REJECT_ST_R = crate::BitReader;
+#[doc = "Field `CORE1_DBUS_ACS_MSK_DCACHE_ST` reader - The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access."]
+pub type CORE1_DBUS_ACS_MSK_DCACHE_ST_R = crate::BitReader;
+#[doc = "Field `CORE1_DBUS_REJECT_ST` reader - The bit is used to indicate interrupt by authentication fail."]
+pub type CORE1_DBUS_REJECT_ST_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_ibus_acs_msk_icache_st(&self) -> CORE1_IBUS_ACS_MSK_ICACHE_ST_R {
+        CORE1_IBUS_ACS_MSK_ICACHE_ST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate interrupt by ibus trying to write icache"]
+    #[inline(always)]
+    pub fn core1_ibus_wr_icache_st(&self) -> CORE1_IBUS_WR_ICACHE_ST_R {
+        CORE1_IBUS_WR_ICACHE_ST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_ibus_reject_st(&self) -> CORE1_IBUS_REJECT_ST_R {
+        CORE1_IBUS_REJECT_ST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access."]
+    #[inline(always)]
+    pub fn core1_dbus_acs_msk_dcache_st(&self) -> CORE1_DBUS_ACS_MSK_DCACHE_ST_R {
+        CORE1_DBUS_ACS_MSK_DCACHE_ST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bit is used to indicate interrupt by authentication fail."]
+    #[inline(always)]
+    pub fn core1_dbus_reject_st(&self) -> CORE1_DBUS_REJECT_ST_R {
+        CORE1_DBUS_REJECT_ST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE1_ACS_CACHE_INT_ST")
+            .field(
+                "core1_ibus_acs_msk_icache_st",
+                &self.core1_ibus_acs_msk_icache_st(),
+            )
+            .field("core1_ibus_wr_icache_st", &self.core1_ibus_wr_icache_st())
+            .field("core1_ibus_reject_st", &self.core1_ibus_reject_st())
+            .field(
+                "core1_dbus_acs_msk_dcache_st",
+                &self.core1_dbus_acs_msk_dcache_st(),
+            )
+            .field("core1_dbus_reject_st", &self.core1_dbus_reject_st())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_acs_cache_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_ACS_CACHE_INT_ST_SPEC;
+impl crate::RegisterSpec for CORE1_ACS_CACHE_INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core1_acs_cache_int_st::R`](R) reader structure"]
+impl crate::Readable for CORE1_ACS_CACHE_INT_ST_SPEC {}
+#[doc = "`reset()` method sets CORE1_ACS_CACHE_INT_ST to value 0"]
+impl crate::Resettable for CORE1_ACS_CACHE_INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core1_dbus_reject_st.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `CORE1_DBUS_REJECT_ST` reader"]
+pub type R = crate::R<CORE1_DBUS_REJECT_ST_SPEC>;
+#[doc = "Field `CORE1_DBUS_TAG_ATTR` reader - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+pub type CORE1_DBUS_TAG_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE1_DBUS_ATTR` reader - The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+pub type CORE1_DBUS_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE1_DBUS_WORLD` reader - The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1"]
+pub type CORE1_DBUS_WORLD_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:2 - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+    #[inline(always)]
+    pub fn core1_dbus_tag_attr(&self) -> CORE1_DBUS_TAG_ATTR_R {
+        CORE1_DBUS_TAG_ATTR_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+    #[inline(always)]
+    pub fn core1_dbus_attr(&self) -> CORE1_DBUS_ATTR_R {
+        CORE1_DBUS_ATTR_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1"]
+    #[inline(always)]
+    pub fn core1_dbus_world(&self) -> CORE1_DBUS_WORLD_R {
+        CORE1_DBUS_WORLD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE1_DBUS_REJECT_ST")
+            .field("core1_dbus_tag_attr", &self.core1_dbus_tag_attr())
+            .field("core1_dbus_attr", &self.core1_dbus_attr())
+            .field("core1_dbus_world", &self.core1_dbus_world())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_dbus_reject_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_DBUS_REJECT_ST_SPEC;
+impl crate::RegisterSpec for CORE1_DBUS_REJECT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core1_dbus_reject_st::R`](R) reader structure"]
+impl crate::Readable for CORE1_DBUS_REJECT_ST_SPEC {}
+#[doc = "`reset()` method sets CORE1_DBUS_REJECT_ST to value 0"]
+impl crate::Resettable for CORE1_DBUS_REJECT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core1_dbus_reject_vaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE1_DBUS_REJECT_VADDR` reader"]
+pub type R = crate::R<CORE1_DBUS_REJECT_VADDR_SPEC>;
+#[doc = "Field `CORE1_DBUS_VADDR` reader - The bits are used to indicate the virtual address of CPU access dbus when authentication fail."]
+pub type CORE1_DBUS_VADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to indicate the virtual address of CPU access dbus when authentication fail."]
+    #[inline(always)]
+    pub fn core1_dbus_vaddr(&self) -> CORE1_DBUS_VADDR_R {
+        CORE1_DBUS_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE1_DBUS_REJECT_VADDR")
+            .field("core1_dbus_vaddr", &self.core1_dbus_vaddr())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_dbus_reject_vaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_DBUS_REJECT_VADDR_SPEC;
+impl crate::RegisterSpec for CORE1_DBUS_REJECT_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core1_dbus_reject_vaddr::R`](R) reader structure"]
+impl crate::Readable for CORE1_DBUS_REJECT_VADDR_SPEC {}
+#[doc = "`reset()` method sets CORE1_DBUS_REJECT_VADDR to value 0xffff_ffff"]
+impl crate::Resettable for CORE1_DBUS_REJECT_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/extmem/core1_ibus_reject_st.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `CORE1_IBUS_REJECT_ST` reader"]
+pub type R = crate::R<CORE1_IBUS_REJECT_ST_SPEC>;
+#[doc = "Field `CORE1_IBUS_TAG_ATTR` reader - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+pub type CORE1_IBUS_TAG_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE1_IBUS_ATTR` reader - The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able"]
+pub type CORE1_IBUS_ATTR_R = crate::FieldReader;
+#[doc = "Field `CORE1_IBUS_WORLD` reader - The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1"]
+pub type CORE1_IBUS_WORLD_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:2 - The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able."]
+    #[inline(always)]
+    pub fn core1_ibus_tag_attr(&self) -> CORE1_IBUS_TAG_ATTR_R {
+        CORE1_IBUS_TAG_ATTR_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able"]
+    #[inline(always)]
+    pub fn core1_ibus_attr(&self) -> CORE1_IBUS_ATTR_R {
+        CORE1_IBUS_ATTR_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1"]
+    #[inline(always)]
+    pub fn core1_ibus_world(&self) -> CORE1_IBUS_WORLD_R {
+        CORE1_IBUS_WORLD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE1_IBUS_REJECT_ST")
+            .field("core1_ibus_tag_attr", &self.core1_ibus_tag_attr())
+            .field("core1_ibus_attr", &self.core1_ibus_attr())
+            .field("core1_ibus_world", &self.core1_ibus_world())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_ibus_reject_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_IBUS_REJECT_ST_SPEC;
+impl crate::RegisterSpec for CORE1_IBUS_REJECT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core1_ibus_reject_st::R`](R) reader structure"]
+impl crate::Readable for CORE1_IBUS_REJECT_ST_SPEC {}
+#[doc = "`reset()` method sets CORE1_IBUS_REJECT_ST to value 0"]
+impl crate::Resettable for CORE1_IBUS_REJECT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/core1_ibus_reject_vaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE1_IBUS_REJECT_VADDR` reader"]
+pub type R = crate::R<CORE1_IBUS_REJECT_VADDR_SPEC>;
+#[doc = "Field `CORE1_IBUS_VADDR` reader - The bits are used to indicate the virtual address of CPU access ibus when authentication fail."]
+pub type CORE1_IBUS_VADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to indicate the virtual address of CPU access ibus when authentication fail."]
+    #[inline(always)]
+    pub fn core1_ibus_vaddr(&self) -> CORE1_IBUS_VADDR_R {
+        CORE1_IBUS_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE1_IBUS_REJECT_VADDR")
+            .field("core1_ibus_vaddr", &self.core1_ibus_vaddr())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_ibus_reject_vaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE1_IBUS_REJECT_VADDR_SPEC;
+impl crate::RegisterSpec for CORE1_IBUS_REJECT_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core1_ibus_reject_vaddr::R`](R) reader structure"]
+impl crate::Readable for CORE1_IBUS_REJECT_VADDR_SPEC {}
+#[doc = "`reset()` method sets CORE1_IBUS_REJECT_VADDR to value 0xffff_ffff"]
+impl crate::Resettable for CORE1_IBUS_REJECT_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/extmem/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - version information."]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - version information."]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - version information."]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - version information."]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0201_2310"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0201_2310;
+}

vendor/esp32s3/src/extmem/dbus_acs_cnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `DBUS_ACS_CNT` reader"]
+pub type R = crate::R<DBUS_ACS_CNT_SPEC>;
+#[doc = "Field `DBUS_ACS_CNT` reader - The bits are used to count the number of dbus access flash/spiram through dcache."]
+pub type DBUS_ACS_CNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to count the number of dbus access flash/spiram through dcache."]
+    #[inline(always)]
+    pub fn dbus_acs_cnt(&self) -> DBUS_ACS_CNT_R {
+        DBUS_ACS_CNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DBUS_ACS_CNT")
+            .field("dbus_acs_cnt", &self.dbus_acs_cnt())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_acs_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DBUS_ACS_CNT_SPEC;
+impl crate::RegisterSpec for DBUS_ACS_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dbus_acs_cnt::R`](R) reader structure"]
+impl crate::Readable for DBUS_ACS_CNT_SPEC {}
+#[doc = "`reset()` method sets DBUS_ACS_CNT to value 0"]
+impl crate::Resettable for DBUS_ACS_CNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dbus_acs_flash_miss_cnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `DBUS_ACS_FLASH_MISS_CNT` reader"]
+pub type R = crate::R<DBUS_ACS_FLASH_MISS_CNT_SPEC>;
+#[doc = "Field `DBUS_ACS_FLASH_MISS_CNT` reader - The bits are used to count the number of the cache miss caused by dbus access flash."]
+pub type DBUS_ACS_FLASH_MISS_CNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to count the number of the cache miss caused by dbus access flash."]
+    #[inline(always)]
+    pub fn dbus_acs_flash_miss_cnt(&self) -> DBUS_ACS_FLASH_MISS_CNT_R {
+        DBUS_ACS_FLASH_MISS_CNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DBUS_ACS_FLASH_MISS_CNT")
+            .field("dbus_acs_flash_miss_cnt", &self.dbus_acs_flash_miss_cnt())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_acs_flash_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DBUS_ACS_FLASH_MISS_CNT_SPEC;
+impl crate::RegisterSpec for DBUS_ACS_FLASH_MISS_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dbus_acs_flash_miss_cnt::R`](R) reader structure"]
+impl crate::Readable for DBUS_ACS_FLASH_MISS_CNT_SPEC {}
+#[doc = "`reset()` method sets DBUS_ACS_FLASH_MISS_CNT to value 0"]
+impl crate::Resettable for DBUS_ACS_FLASH_MISS_CNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dbus_acs_spiram_miss_cnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `DBUS_ACS_SPIRAM_MISS_CNT` reader"]
+pub type R = crate::R<DBUS_ACS_SPIRAM_MISS_CNT_SPEC>;
+#[doc = "Field `DBUS_ACS_SPIRAM_MISS_CNT` reader - The bits are used to count the number of the cache miss caused by dbus access spiram."]
+pub type DBUS_ACS_SPIRAM_MISS_CNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to count the number of the cache miss caused by dbus access spiram."]
+    #[inline(always)]
+    pub fn dbus_acs_spiram_miss_cnt(&self) -> DBUS_ACS_SPIRAM_MISS_CNT_R {
+        DBUS_ACS_SPIRAM_MISS_CNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DBUS_ACS_SPIRAM_MISS_CNT")
+            .field("dbus_acs_spiram_miss_cnt", &self.dbus_acs_spiram_miss_cnt())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_acs_spiram_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DBUS_ACS_SPIRAM_MISS_CNT_SPEC;
+impl crate::RegisterSpec for DBUS_ACS_SPIRAM_MISS_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dbus_acs_spiram_miss_cnt::R`](R) reader structure"]
+impl crate::Readable for DBUS_ACS_SPIRAM_MISS_CNT_SPEC {}
+#[doc = "`reset()` method sets DBUS_ACS_SPIRAM_MISS_CNT to value 0"]
+impl crate::Resettable for DBUS_ACS_SPIRAM_MISS_CNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `DBUS_TO_FLASH_END_VADDR` reader"]
+pub type R = crate::R<DBUS_TO_FLASH_END_VADDR_SPEC>;
+#[doc = "Register `DBUS_TO_FLASH_END_VADDR` writer"]
+pub type W = crate::W<DBUS_TO_FLASH_END_VADDR_SPEC>;
+#[doc = "Field `DBUS_TO_FLASH_END_VADDR` reader - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+pub type DBUS_TO_FLASH_END_VADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DBUS_TO_FLASH_END_VADDR` writer - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+pub type DBUS_TO_FLASH_END_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+    #[inline(always)]
+    pub fn dbus_to_flash_end_vaddr(&self) -> DBUS_TO_FLASH_END_VADDR_R {
+        DBUS_TO_FLASH_END_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DBUS_TO_FLASH_END_VADDR")
+            .field("dbus_to_flash_end_vaddr", &self.dbus_to_flash_end_vaddr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+    #[inline(always)]
+    pub fn dbus_to_flash_end_vaddr(
+        &mut self,
+    ) -> DBUS_TO_FLASH_END_VADDR_W<DBUS_TO_FLASH_END_VADDR_SPEC> {
+        DBUS_TO_FLASH_END_VADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_to_flash_end_vaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbus_to_flash_end_vaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DBUS_TO_FLASH_END_VADDR_SPEC;
+impl crate::RegisterSpec for DBUS_TO_FLASH_END_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dbus_to_flash_end_vaddr::R`](R) reader structure"]
+impl crate::Readable for DBUS_TO_FLASH_END_VADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dbus_to_flash_end_vaddr::W`](W) writer structure"]
+impl crate::Writable for DBUS_TO_FLASH_END_VADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DBUS_TO_FLASH_END_VADDR to value 0"]
+impl crate::Resettable for DBUS_TO_FLASH_END_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `DBUS_TO_FLASH_START_VADDR` reader"]
+pub type R = crate::R<DBUS_TO_FLASH_START_VADDR_SPEC>;
+#[doc = "Register `DBUS_TO_FLASH_START_VADDR` writer"]
+pub type W = crate::W<DBUS_TO_FLASH_START_VADDR_SPEC>;
+#[doc = "Field `DBUS_TO_FLASH_START_VADDR` reader - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+pub type DBUS_TO_FLASH_START_VADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DBUS_TO_FLASH_START_VADDR` writer - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+pub type DBUS_TO_FLASH_START_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+    #[inline(always)]
+    pub fn dbus_to_flash_start_vaddr(&self) -> DBUS_TO_FLASH_START_VADDR_R {
+        DBUS_TO_FLASH_START_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DBUS_TO_FLASH_START_VADDR")
+            .field(
+                "dbus_to_flash_start_vaddr",
+                &self.dbus_to_flash_start_vaddr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
+    #[inline(always)]
+    pub fn dbus_to_flash_start_vaddr(
+        &mut self,
+    ) -> DBUS_TO_FLASH_START_VADDR_W<DBUS_TO_FLASH_START_VADDR_SPEC> {
+        DBUS_TO_FLASH_START_VADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_to_flash_start_vaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbus_to_flash_start_vaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DBUS_TO_FLASH_START_VADDR_SPEC;
+impl crate::RegisterSpec for DBUS_TO_FLASH_START_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dbus_to_flash_start_vaddr::R`](R) reader structure"]
+impl crate::Readable for DBUS_TO_FLASH_START_VADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dbus_to_flash_start_vaddr::W`](W) writer structure"]
+impl crate::Writable for DBUS_TO_FLASH_START_VADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DBUS_TO_FLASH_START_VADDR to value 0"]
+impl crate::Resettable for DBUS_TO_FLASH_START_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_atomic_operate_ena.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `DCACHE_ATOMIC_OPERATE_ENA` reader"]
+pub type R = crate::R<DCACHE_ATOMIC_OPERATE_ENA_SPEC>;
+#[doc = "Register `DCACHE_ATOMIC_OPERATE_ENA` writer"]
+pub type W = crate::W<DCACHE_ATOMIC_OPERATE_ENA_SPEC>;
+#[doc = "Field `DCACHE_ATOMIC_OPERATE_ENA` reader - The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+pub type DCACHE_ATOMIC_OPERATE_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_ATOMIC_OPERATE_ENA` writer - The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+pub type DCACHE_ATOMIC_OPERATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+    #[inline(always)]
+    pub fn dcache_atomic_operate_ena(&self) -> DCACHE_ATOMIC_OPERATE_ENA_R {
+        DCACHE_ATOMIC_OPERATE_ENA_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_ATOMIC_OPERATE_ENA")
+            .field(
+                "dcache_atomic_operate_ena",
+                &self.dcache_atomic_operate_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+    #[inline(always)]
+    pub fn dcache_atomic_operate_ena(
+        &mut self,
+    ) -> DCACHE_ATOMIC_OPERATE_ENA_W<DCACHE_ATOMIC_OPERATE_ENA_SPEC> {
+        DCACHE_ATOMIC_OPERATE_ENA_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_atomic_operate_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_atomic_operate_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_ATOMIC_OPERATE_ENA_SPEC;
+impl crate::RegisterSpec for DCACHE_ATOMIC_OPERATE_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_atomic_operate_ena::R`](R) reader structure"]
+impl crate::Readable for DCACHE_ATOMIC_OPERATE_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_atomic_operate_ena::W`](W) writer structure"]
+impl crate::Writable for DCACHE_ATOMIC_OPERATE_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_ATOMIC_OPERATE_ENA to value 0x01"]
+impl crate::Resettable for DCACHE_ATOMIC_OPERATE_ENA_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/extmem/dcache_autoload_ctrl.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `DCACHE_AUTOLOAD_CTRL` reader"]
+pub type R = crate::R<DCACHE_AUTOLOAD_CTRL_SPEC>;
+#[doc = "Register `DCACHE_AUTOLOAD_CTRL` writer"]
+pub type W = crate::W<DCACHE_AUTOLOAD_CTRL_SPEC>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT0_ENA` reader - The bits are used to enable the first section for autoload operation."]
+pub type DCACHE_AUTOLOAD_SCT0_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT0_ENA` writer - The bits are used to enable the first section for autoload operation."]
+pub type DCACHE_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT1_ENA` reader - The bits are used to enable the second section for autoload operation."]
+pub type DCACHE_AUTOLOAD_SCT1_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT1_ENA` writer - The bits are used to enable the second section for autoload operation."]
+pub type DCACHE_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable."]
+pub type DCACHE_AUTOLOAD_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_AUTOLOAD_ENA` writer - The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable."]
+pub type DCACHE_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_AUTOLOAD_DONE` reader - The bit is used to indicate autoload operation is finished."]
+pub type DCACHE_AUTOLOAD_DONE_R = crate::BitReader;
+#[doc = "Field `DCACHE_AUTOLOAD_ORDER` reader - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+pub type DCACHE_AUTOLOAD_ORDER_R = crate::BitReader;
+#[doc = "Field `DCACHE_AUTOLOAD_ORDER` writer - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+pub type DCACHE_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_AUTOLOAD_RQST` reader - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+pub type DCACHE_AUTOLOAD_RQST_R = crate::FieldReader;
+#[doc = "Field `DCACHE_AUTOLOAD_RQST` writer - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+pub type DCACHE_AUTOLOAD_RQST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DCACHE_AUTOLOAD_SIZE` reader - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+pub type DCACHE_AUTOLOAD_SIZE_R = crate::FieldReader;
+#[doc = "Field `DCACHE_AUTOLOAD_SIZE` writer - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+pub type DCACHE_AUTOLOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DCACHE_AUTOLOAD_BUFFER_CLEAR` reader - The bit is used to clear autoload buffer in dcache."]
+pub type DCACHE_AUTOLOAD_BUFFER_CLEAR_R = crate::BitReader;
+#[doc = "Field `DCACHE_AUTOLOAD_BUFFER_CLEAR` writer - The bit is used to clear autoload buffer in dcache."]
+pub type DCACHE_AUTOLOAD_BUFFER_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct0_ena(&self) -> DCACHE_AUTOLOAD_SCT0_ENA_R {
+        DCACHE_AUTOLOAD_SCT0_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bits are used to enable the second section for autoload operation."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct1_ena(&self) -> DCACHE_AUTOLOAD_SCT1_ENA_R {
+        DCACHE_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable."]
+    #[inline(always)]
+    pub fn dcache_autoload_ena(&self) -> DCACHE_AUTOLOAD_ENA_R {
+        DCACHE_AUTOLOAD_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate autoload operation is finished."]
+    #[inline(always)]
+    pub fn dcache_autoload_done(&self) -> DCACHE_AUTOLOAD_DONE_R {
+        DCACHE_AUTOLOAD_DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn dcache_autoload_order(&self) -> DCACHE_AUTOLOAD_ORDER_R {
+        DCACHE_AUTOLOAD_ORDER_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+    #[inline(always)]
+    pub fn dcache_autoload_rqst(&self) -> DCACHE_AUTOLOAD_RQST_R {
+        DCACHE_AUTOLOAD_RQST_R::new(((self.bits >> 5) & 3) as u8)
+    }
+    #[doc = "Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+    #[inline(always)]
+    pub fn dcache_autoload_size(&self) -> DCACHE_AUTOLOAD_SIZE_R {
+        DCACHE_AUTOLOAD_SIZE_R::new(((self.bits >> 7) & 3) as u8)
+    }
+    #[doc = "Bit 9 - The bit is used to clear autoload buffer in dcache."]
+    #[inline(always)]
+    pub fn dcache_autoload_buffer_clear(&self) -> DCACHE_AUTOLOAD_BUFFER_CLEAR_R {
+        DCACHE_AUTOLOAD_BUFFER_CLEAR_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_AUTOLOAD_CTRL")
+            .field("dcache_autoload_sct0_ena", &self.dcache_autoload_sct0_ena())
+            .field("dcache_autoload_sct1_ena", &self.dcache_autoload_sct1_ena())
+            .field("dcache_autoload_ena", &self.dcache_autoload_ena())
+            .field("dcache_autoload_done", &self.dcache_autoload_done())
+            .field("dcache_autoload_order", &self.dcache_autoload_order())
+            .field("dcache_autoload_rqst", &self.dcache_autoload_rqst())
+            .field("dcache_autoload_size", &self.dcache_autoload_size())
+            .field(
+                "dcache_autoload_buffer_clear",
+                &self.dcache_autoload_buffer_clear(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct0_ena(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_SCT0_ENA_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_SCT0_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bits are used to enable the second section for autoload operation."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct1_ena(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_SCT1_ENA_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_SCT1_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable."]
+    #[inline(always)]
+    pub fn dcache_autoload_ena(&mut self) -> DCACHE_AUTOLOAD_ENA_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn dcache_autoload_order(&mut self) -> DCACHE_AUTOLOAD_ORDER_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_ORDER_W::new(self, 4)
+    }
+    #[doc = "Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+    #[inline(always)]
+    pub fn dcache_autoload_rqst(&mut self) -> DCACHE_AUTOLOAD_RQST_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_RQST_W::new(self, 5)
+    }
+    #[doc = "Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+    #[inline(always)]
+    pub fn dcache_autoload_size(&mut self) -> DCACHE_AUTOLOAD_SIZE_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_SIZE_W::new(self, 7)
+    }
+    #[doc = "Bit 9 - The bit is used to clear autoload buffer in dcache."]
+    #[inline(always)]
+    pub fn dcache_autoload_buffer_clear(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_BUFFER_CLEAR_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
+        DCACHE_AUTOLOAD_BUFFER_CLEAR_W::new(self, 9)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_AUTOLOAD_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_AUTOLOAD_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_autoload_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_AUTOLOAD_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_autoload_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_AUTOLOAD_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_AUTOLOAD_CTRL to value 0x08"]
+impl crate::Resettable for DCACHE_AUTOLOAD_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x08;
+}

vendor/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `DCACHE_AUTOLOAD_SCT0_ADDR` reader"]
+pub type R = crate::R<DCACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
+#[doc = "Register `DCACHE_AUTOLOAD_SCT0_ADDR` writer"]
+pub type W = crate::W<DCACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT0_ADDR` reader - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+pub type DCACHE_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT0_ADDR` writer - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+pub type DCACHE_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct0_addr(&self) -> DCACHE_AUTOLOAD_SCT0_ADDR_R {
+        DCACHE_AUTOLOAD_SCT0_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_AUTOLOAD_SCT0_ADDR")
+            .field(
+                "dcache_autoload_sct0_addr",
+                &self.dcache_autoload_sct0_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct0_addr(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_SCT0_ADDR_W<DCACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
+        DCACHE_AUTOLOAD_SCT0_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_AUTOLOAD_SCT0_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_AUTOLOAD_SCT0_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_autoload_sct0_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_AUTOLOAD_SCT0_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_autoload_sct0_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_AUTOLOAD_SCT0_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_AUTOLOAD_SCT0_ADDR to value 0"]
+impl crate::Resettable for DCACHE_AUTOLOAD_SCT0_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_autoload_sct0_size.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `DCACHE_AUTOLOAD_SCT0_SIZE` reader"]
+pub type R = crate::R<DCACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
+#[doc = "Register `DCACHE_AUTOLOAD_SCT0_SIZE` writer"]
+pub type W = crate::W<DCACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT0_SIZE` reader - The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+pub type DCACHE_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT0_SIZE` writer - The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+pub type DCACHE_AUTOLOAD_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
+impl R {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct0_size(&self) -> DCACHE_AUTOLOAD_SCT0_SIZE_R {
+        DCACHE_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x07ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_AUTOLOAD_SCT0_SIZE")
+            .field(
+                "dcache_autoload_sct0_size",
+                &self.dcache_autoload_sct0_size(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct0_size(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_SCT0_SIZE_W<DCACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
+        DCACHE_AUTOLOAD_SCT0_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct0_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct0_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_AUTOLOAD_SCT0_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_AUTOLOAD_SCT0_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_autoload_sct0_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_AUTOLOAD_SCT0_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_autoload_sct0_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_AUTOLOAD_SCT0_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_AUTOLOAD_SCT0_SIZE to value 0"]
+impl crate::Resettable for DCACHE_AUTOLOAD_SCT0_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `DCACHE_AUTOLOAD_SCT1_ADDR` reader"]
+pub type R = crate::R<DCACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
+#[doc = "Register `DCACHE_AUTOLOAD_SCT1_ADDR` writer"]
+pub type W = crate::W<DCACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT1_ADDR` reader - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+pub type DCACHE_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT1_ADDR` writer - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+pub type DCACHE_AUTOLOAD_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct1_addr(&self) -> DCACHE_AUTOLOAD_SCT1_ADDR_R {
+        DCACHE_AUTOLOAD_SCT1_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_AUTOLOAD_SCT1_ADDR")
+            .field(
+                "dcache_autoload_sct1_addr",
+                &self.dcache_autoload_sct1_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct1_addr(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_SCT1_ADDR_W<DCACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
+        DCACHE_AUTOLOAD_SCT1_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_AUTOLOAD_SCT1_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_AUTOLOAD_SCT1_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_autoload_sct1_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_AUTOLOAD_SCT1_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_autoload_sct1_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_AUTOLOAD_SCT1_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_AUTOLOAD_SCT1_ADDR to value 0"]
+impl crate::Resettable for DCACHE_AUTOLOAD_SCT1_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_autoload_sct1_size.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `DCACHE_AUTOLOAD_SCT1_SIZE` reader"]
+pub type R = crate::R<DCACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
+#[doc = "Register `DCACHE_AUTOLOAD_SCT1_SIZE` writer"]
+pub type W = crate::W<DCACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT1_SIZE` reader - The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+pub type DCACHE_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_AUTOLOAD_SCT1_SIZE` writer - The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+pub type DCACHE_AUTOLOAD_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
+impl R {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct1_size(&self) -> DCACHE_AUTOLOAD_SCT1_SIZE_R {
+        DCACHE_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x07ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_AUTOLOAD_SCT1_SIZE")
+            .field(
+                "dcache_autoload_sct1_size",
+                &self.dcache_autoload_sct1_size(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn dcache_autoload_sct1_size(
+        &mut self,
+    ) -> DCACHE_AUTOLOAD_SCT1_SIZE_W<DCACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
+        DCACHE_AUTOLOAD_SCT1_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct1_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct1_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_AUTOLOAD_SCT1_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_AUTOLOAD_SCT1_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_autoload_sct1_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_AUTOLOAD_SCT1_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_autoload_sct1_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_AUTOLOAD_SCT1_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_AUTOLOAD_SCT1_SIZE to value 0"]
+impl crate::Resettable for DCACHE_AUTOLOAD_SCT1_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_ctrl.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `DCACHE_CTRL` reader"]
+pub type R = crate::R<DCACHE_CTRL_SPEC>;
+#[doc = "Register `DCACHE_CTRL` writer"]
+pub type W = crate::W<DCACHE_CTRL_SPEC>;
+#[doc = "Field `DCACHE_ENABLE` reader - The bit is used to activate the data cache. 0: disable, 1: enable"]
+pub type DCACHE_ENABLE_R = crate::BitReader;
+#[doc = "Field `DCACHE_ENABLE` writer - The bit is used to activate the data cache. 0: disable, 1: enable"]
+pub type DCACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_SIZE_MODE` reader - The bit is used to configure cache memory size.0: 32KB, 1: 64KB"]
+pub type DCACHE_SIZE_MODE_R = crate::BitReader;
+#[doc = "Field `DCACHE_SIZE_MODE` writer - The bit is used to configure cache memory size.0: 32KB, 1: 64KB"]
+pub type DCACHE_SIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_BLOCKSIZE_MODE` reader - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes"]
+pub type DCACHE_BLOCKSIZE_MODE_R = crate::FieldReader;
+#[doc = "Field `DCACHE_BLOCKSIZE_MODE` writer - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes"]
+pub type DCACHE_BLOCKSIZE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn dcache_enable(&self) -> DCACHE_ENABLE_R {
+        DCACHE_ENABLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 32KB, 1: 64KB"]
+    #[inline(always)]
+    pub fn dcache_size_mode(&self) -> DCACHE_SIZE_MODE_R {
+        DCACHE_SIZE_MODE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bits 3:4 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes"]
+    #[inline(always)]
+    pub fn dcache_blocksize_mode(&self) -> DCACHE_BLOCKSIZE_MODE_R {
+        DCACHE_BLOCKSIZE_MODE_R::new(((self.bits >> 3) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_CTRL")
+            .field("dcache_enable", &self.dcache_enable())
+            .field("dcache_size_mode", &self.dcache_size_mode())
+            .field("dcache_blocksize_mode", &self.dcache_blocksize_mode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn dcache_enable(&mut self) -> DCACHE_ENABLE_W<DCACHE_CTRL_SPEC> {
+        DCACHE_ENABLE_W::new(self, 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 32KB, 1: 64KB"]
+    #[inline(always)]
+    pub fn dcache_size_mode(&mut self) -> DCACHE_SIZE_MODE_W<DCACHE_CTRL_SPEC> {
+        DCACHE_SIZE_MODE_W::new(self, 2)
+    }
+    #[doc = "Bits 3:4 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes"]
+    #[inline(always)]
+    pub fn dcache_blocksize_mode(&mut self) -> DCACHE_BLOCKSIZE_MODE_W<DCACHE_CTRL_SPEC> {
+        DCACHE_BLOCKSIZE_MODE_W::new(self, 3)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_CTRL to value 0"]
+impl crate::Resettable for DCACHE_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_ctrl1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `DCACHE_CTRL1` reader"]
+pub type R = crate::R<DCACHE_CTRL1_SPEC>;
+#[doc = "Register `DCACHE_CTRL1` writer"]
+pub type W = crate::W<DCACHE_CTRL1_SPEC>;
+#[doc = "Field `DCACHE_SHUT_CORE0_BUS` reader - The bit is used to disable core0 dbus, 0: enable, 1: disable"]
+pub type DCACHE_SHUT_CORE0_BUS_R = crate::BitReader;
+#[doc = "Field `DCACHE_SHUT_CORE0_BUS` writer - The bit is used to disable core0 dbus, 0: enable, 1: disable"]
+pub type DCACHE_SHUT_CORE0_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_SHUT_CORE1_BUS` reader - The bit is used to disable core1 dbus, 0: enable, 1: disable"]
+pub type DCACHE_SHUT_CORE1_BUS_R = crate::BitReader;
+#[doc = "Field `DCACHE_SHUT_CORE1_BUS` writer - The bit is used to disable core1 dbus, 0: enable, 1: disable"]
+pub type DCACHE_SHUT_CORE1_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to disable core0 dbus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn dcache_shut_core0_bus(&self) -> DCACHE_SHUT_CORE0_BUS_R {
+        DCACHE_SHUT_CORE0_BUS_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to disable core1 dbus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn dcache_shut_core1_bus(&self) -> DCACHE_SHUT_CORE1_BUS_R {
+        DCACHE_SHUT_CORE1_BUS_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_CTRL1")
+            .field("dcache_shut_core0_bus", &self.dcache_shut_core0_bus())
+            .field("dcache_shut_core1_bus", &self.dcache_shut_core1_bus())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to disable core0 dbus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn dcache_shut_core0_bus(&mut self) -> DCACHE_SHUT_CORE0_BUS_W<DCACHE_CTRL1_SPEC> {
+        DCACHE_SHUT_CORE0_BUS_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to disable core1 dbus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn dcache_shut_core1_bus(&mut self) -> DCACHE_SHUT_CORE1_BUS_W<DCACHE_CTRL1_SPEC> {
+        DCACHE_SHUT_CORE1_BUS_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_CTRL1_SPEC;
+impl crate::RegisterSpec for DCACHE_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_ctrl1::R`](R) reader structure"]
+impl crate::Readable for DCACHE_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_ctrl1::W`](W) writer structure"]
+impl crate::Writable for DCACHE_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_CTRL1 to value 0x03"]
+impl crate::Resettable for DCACHE_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0x03;
+}

vendor/esp32s3/src/extmem/dcache_freeze.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `DCACHE_FREEZE` reader"]
+pub type R = crate::R<DCACHE_FREEZE_SPEC>;
+#[doc = "Register `DCACHE_FREEZE` writer"]
+pub type W = crate::W<DCACHE_FREEZE_SPEC>;
+#[doc = "Field `ENA` reader - The bit is used to enable dcache freeze mode"]
+pub type ENA_R = crate::BitReader;
+#[doc = "Field `ENA` writer - The bit is used to enable dcache freeze mode"]
+pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MODE` reader - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+pub type MODE_R = crate::BitReader;
+#[doc = "Field `MODE` writer - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DONE` reader - The bit is used to indicate dcache freeze success"]
+pub type DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable dcache freeze mode"]
+    #[inline(always)]
+    pub fn ena(&self) -> ENA_R {
+        ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate dcache freeze success"]
+    #[inline(always)]
+    pub fn done(&self) -> DONE_R {
+        DONE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_FREEZE")
+            .field("ena", &self.ena())
+            .field("mode", &self.mode())
+            .field("done", &self.done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable dcache freeze mode"]
+    #[inline(always)]
+    pub fn ena(&mut self) -> ENA_W<DCACHE_FREEZE_SPEC> {
+        ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<DCACHE_FREEZE_SPEC> {
+        MODE_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_freeze::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_freeze::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_FREEZE_SPEC;
+impl crate::RegisterSpec for DCACHE_FREEZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_freeze::R`](R) reader structure"]
+impl crate::Readable for DCACHE_FREEZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_freeze::W`](W) writer structure"]
+impl crate::Writable for DCACHE_FREEZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_FREEZE to value 0x04"]
+impl crate::Resettable for DCACHE_FREEZE_SPEC {
+    const RESET_VALUE: u32 = 0x04;
+}

vendor/esp32s3/src/extmem/dcache_lock_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_LOCK_ADDR` reader"]
+pub type R = crate::R<DCACHE_LOCK_ADDR_SPEC>;
+#[doc = "Register `DCACHE_LOCK_ADDR` writer"]
+pub type W = crate::W<DCACHE_LOCK_ADDR_SPEC>;
+#[doc = "Field `DCACHE_LOCK_ADDR` reader - The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG."]
+pub type DCACHE_LOCK_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_LOCK_ADDR` writer - The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG."]
+pub type DCACHE_LOCK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_lock_addr(&self) -> DCACHE_LOCK_ADDR_R {
+        DCACHE_LOCK_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_LOCK_ADDR")
+            .field("dcache_lock_addr", &self.dcache_lock_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_lock_addr(&mut self) -> DCACHE_LOCK_ADDR_W<DCACHE_LOCK_ADDR_SPEC> {
+        DCACHE_LOCK_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_lock_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_lock_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_LOCK_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_LOCK_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_lock_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_LOCK_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_lock_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_LOCK_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_LOCK_ADDR to value 0"]
+impl crate::Resettable for DCACHE_LOCK_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_lock_ctrl.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `DCACHE_LOCK_CTRL` reader"]
+pub type R = crate::R<DCACHE_LOCK_CTRL_SPEC>;
+#[doc = "Register `DCACHE_LOCK_CTRL` writer"]
+pub type W = crate::W<DCACHE_LOCK_CTRL_SPEC>;
+#[doc = "Field `DCACHE_LOCK_ENA` reader - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+pub type DCACHE_LOCK_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_LOCK_ENA` writer - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+pub type DCACHE_LOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_UNLOCK_ENA` reader - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+pub type DCACHE_UNLOCK_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_UNLOCK_ENA` writer - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+pub type DCACHE_UNLOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_LOCK_DONE` reader - The bit is used to indicate unlock/lock operation is finished."]
+pub type DCACHE_LOCK_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+    #[inline(always)]
+    pub fn dcache_lock_ena(&self) -> DCACHE_LOCK_ENA_R {
+        DCACHE_LOCK_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+    #[inline(always)]
+    pub fn dcache_unlock_ena(&self) -> DCACHE_UNLOCK_ENA_R {
+        DCACHE_UNLOCK_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate unlock/lock operation is finished."]
+    #[inline(always)]
+    pub fn dcache_lock_done(&self) -> DCACHE_LOCK_DONE_R {
+        DCACHE_LOCK_DONE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_LOCK_CTRL")
+            .field("dcache_lock_ena", &self.dcache_lock_ena())
+            .field("dcache_unlock_ena", &self.dcache_unlock_ena())
+            .field("dcache_lock_done", &self.dcache_lock_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+    #[inline(always)]
+    pub fn dcache_lock_ena(&mut self) -> DCACHE_LOCK_ENA_W<DCACHE_LOCK_CTRL_SPEC> {
+        DCACHE_LOCK_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+    #[inline(always)]
+    pub fn dcache_unlock_ena(&mut self) -> DCACHE_UNLOCK_ENA_W<DCACHE_LOCK_CTRL_SPEC> {
+        DCACHE_UNLOCK_ENA_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_LOCK_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_LOCK_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_lock_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_LOCK_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_lock_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_LOCK_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_LOCK_CTRL to value 0x04"]
+impl crate::Resettable for DCACHE_LOCK_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x04;
+}

vendor/esp32s3/src/extmem/dcache_lock_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_LOCK_SIZE` reader"]
+pub type R = crate::R<DCACHE_LOCK_SIZE_SPEC>;
+#[doc = "Register `DCACHE_LOCK_SIZE` writer"]
+pub type W = crate::W<DCACHE_LOCK_SIZE_SPEC>;
+#[doc = "Field `DCACHE_LOCK_SIZE` reader - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG."]
+pub type DCACHE_LOCK_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `DCACHE_LOCK_SIZE` writer - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG."]
+pub type DCACHE_LOCK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG."]
+    #[inline(always)]
+    pub fn dcache_lock_size(&self) -> DCACHE_LOCK_SIZE_R {
+        DCACHE_LOCK_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_LOCK_SIZE")
+            .field("dcache_lock_size", &self.dcache_lock_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG."]
+    #[inline(always)]
+    pub fn dcache_lock_size(&mut self) -> DCACHE_LOCK_SIZE_W<DCACHE_LOCK_SIZE_SPEC> {
+        DCACHE_LOCK_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_lock_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_lock_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_LOCK_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_LOCK_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_lock_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_LOCK_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_lock_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_LOCK_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_LOCK_SIZE to value 0"]
+impl crate::Resettable for DCACHE_LOCK_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_occupy_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_OCCUPY_ADDR` reader"]
+pub type R = crate::R<DCACHE_OCCUPY_ADDR_SPEC>;
+#[doc = "Register `DCACHE_OCCUPY_ADDR` writer"]
+pub type W = crate::W<DCACHE_OCCUPY_ADDR_SPEC>;
+#[doc = "Field `DCACHE_OCCUPY_ADDR` reader - The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG."]
+pub type DCACHE_OCCUPY_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_OCCUPY_ADDR` writer - The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG."]
+pub type DCACHE_OCCUPY_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_occupy_addr(&self) -> DCACHE_OCCUPY_ADDR_R {
+        DCACHE_OCCUPY_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_OCCUPY_ADDR")
+            .field("dcache_occupy_addr", &self.dcache_occupy_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_occupy_addr(&mut self) -> DCACHE_OCCUPY_ADDR_W<DCACHE_OCCUPY_ADDR_SPEC> {
+        DCACHE_OCCUPY_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_occupy_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_occupy_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_OCCUPY_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_OCCUPY_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_occupy_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_OCCUPY_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_occupy_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_OCCUPY_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_OCCUPY_ADDR to value 0"]
+impl crate::Resettable for DCACHE_OCCUPY_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_occupy_ctrl.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DCACHE_OCCUPY_CTRL` reader"]
+pub type R = crate::R<DCACHE_OCCUPY_CTRL_SPEC>;
+#[doc = "Register `DCACHE_OCCUPY_CTRL` writer"]
+pub type W = crate::W<DCACHE_OCCUPY_CTRL_SPEC>;
+#[doc = "Field `DCACHE_OCCUPY_ENA` reader - The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation."]
+pub type DCACHE_OCCUPY_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_OCCUPY_ENA` writer - The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation."]
+pub type DCACHE_OCCUPY_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_OCCUPY_DONE` reader - The bit is used to indicate occupy operation is finished."]
+pub type DCACHE_OCCUPY_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation."]
+    #[inline(always)]
+    pub fn dcache_occupy_ena(&self) -> DCACHE_OCCUPY_ENA_R {
+        DCACHE_OCCUPY_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate occupy operation is finished."]
+    #[inline(always)]
+    pub fn dcache_occupy_done(&self) -> DCACHE_OCCUPY_DONE_R {
+        DCACHE_OCCUPY_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_OCCUPY_CTRL")
+            .field("dcache_occupy_ena", &self.dcache_occupy_ena())
+            .field("dcache_occupy_done", &self.dcache_occupy_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation."]
+    #[inline(always)]
+    pub fn dcache_occupy_ena(&mut self) -> DCACHE_OCCUPY_ENA_W<DCACHE_OCCUPY_CTRL_SPEC> {
+        DCACHE_OCCUPY_ENA_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_occupy_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_occupy_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_OCCUPY_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_OCCUPY_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_occupy_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_OCCUPY_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_occupy_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_OCCUPY_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_OCCUPY_CTRL to value 0x02"]
+impl crate::Resettable for DCACHE_OCCUPY_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x02;
+}

vendor/esp32s3/src/extmem/dcache_occupy_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_OCCUPY_SIZE` reader"]
+pub type R = crate::R<DCACHE_OCCUPY_SIZE_SPEC>;
+#[doc = "Register `DCACHE_OCCUPY_SIZE` writer"]
+pub type W = crate::W<DCACHE_OCCUPY_SIZE_SPEC>;
+#[doc = "Field `DCACHE_OCCUPY_SIZE` reader - The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG."]
+pub type DCACHE_OCCUPY_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `DCACHE_OCCUPY_SIZE` writer - The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG."]
+pub type DCACHE_OCCUPY_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG."]
+    #[inline(always)]
+    pub fn dcache_occupy_size(&self) -> DCACHE_OCCUPY_SIZE_R {
+        DCACHE_OCCUPY_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_OCCUPY_SIZE")
+            .field("dcache_occupy_size", &self.dcache_occupy_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG."]
+    #[inline(always)]
+    pub fn dcache_occupy_size(&mut self) -> DCACHE_OCCUPY_SIZE_W<DCACHE_OCCUPY_SIZE_SPEC> {
+        DCACHE_OCCUPY_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_occupy_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_occupy_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_OCCUPY_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_OCCUPY_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_occupy_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_OCCUPY_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_occupy_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_OCCUPY_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_OCCUPY_SIZE to value 0"]
+impl crate::Resettable for DCACHE_OCCUPY_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_preload_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_PRELOAD_ADDR` reader"]
+pub type R = crate::R<DCACHE_PRELOAD_ADDR_SPEC>;
+#[doc = "Register `DCACHE_PRELOAD_ADDR` writer"]
+pub type W = crate::W<DCACHE_PRELOAD_ADDR_SPEC>;
+#[doc = "Field `DCACHE_PRELOAD_ADDR` reader - The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG."]
+pub type DCACHE_PRELOAD_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_PRELOAD_ADDR` writer - The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG."]
+pub type DCACHE_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_preload_addr(&self) -> DCACHE_PRELOAD_ADDR_R {
+        DCACHE_PRELOAD_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOAD_ADDR")
+            .field("dcache_preload_addr", &self.dcache_preload_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_preload_addr(&mut self) -> DCACHE_PRELOAD_ADDR_W<DCACHE_PRELOAD_ADDR_SPEC> {
+        DCACHE_PRELOAD_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_preload_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_preload_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOAD_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOAD_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_preload_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOAD_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_preload_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOAD_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOAD_ADDR to value 0"]
+impl crate::Resettable for DCACHE_PRELOAD_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_preload_ctrl.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `DCACHE_PRELOAD_CTRL` reader"]
+pub type R = crate::R<DCACHE_PRELOAD_CTRL_SPEC>;
+#[doc = "Register `DCACHE_PRELOAD_CTRL` writer"]
+pub type W = crate::W<DCACHE_PRELOAD_CTRL_SPEC>;
+#[doc = "Field `DCACHE_PRELOAD_ENA` reader - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+pub type DCACHE_PRELOAD_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_ENA` writer - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+pub type DCACHE_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_PRELOAD_DONE` reader - The bit is used to indicate preload operation is finished."]
+pub type DCACHE_PRELOAD_DONE_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+pub type DCACHE_PRELOAD_ORDER_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+pub type DCACHE_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+    #[inline(always)]
+    pub fn dcache_preload_ena(&self) -> DCACHE_PRELOAD_ENA_R {
+        DCACHE_PRELOAD_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate preload operation is finished."]
+    #[inline(always)]
+    pub fn dcache_preload_done(&self) -> DCACHE_PRELOAD_DONE_R {
+        DCACHE_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn dcache_preload_order(&self) -> DCACHE_PRELOAD_ORDER_R {
+        DCACHE_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOAD_CTRL")
+            .field("dcache_preload_ena", &self.dcache_preload_ena())
+            .field("dcache_preload_done", &self.dcache_preload_done())
+            .field("dcache_preload_order", &self.dcache_preload_order())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+    #[inline(always)]
+    pub fn dcache_preload_ena(&mut self) -> DCACHE_PRELOAD_ENA_W<DCACHE_PRELOAD_CTRL_SPEC> {
+        DCACHE_PRELOAD_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn dcache_preload_order(&mut self) -> DCACHE_PRELOAD_ORDER_W<DCACHE_PRELOAD_CTRL_SPEC> {
+        DCACHE_PRELOAD_ORDER_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_preload_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_preload_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOAD_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOAD_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_preload_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOAD_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_preload_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOAD_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOAD_CTRL to value 0x02"]
+impl crate::Resettable for DCACHE_PRELOAD_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x02;
+}

vendor/esp32s3/src/extmem/dcache_preload_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_PRELOAD_SIZE` reader"]
+pub type R = crate::R<DCACHE_PRELOAD_SIZE_SPEC>;
+#[doc = "Register `DCACHE_PRELOAD_SIZE` writer"]
+pub type W = crate::W<DCACHE_PRELOAD_SIZE_SPEC>;
+#[doc = "Field `DCACHE_PRELOAD_SIZE` reader - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.."]
+pub type DCACHE_PRELOAD_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `DCACHE_PRELOAD_SIZE` writer - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.."]
+pub type DCACHE_PRELOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.."]
+    #[inline(always)]
+    pub fn dcache_preload_size(&self) -> DCACHE_PRELOAD_SIZE_R {
+        DCACHE_PRELOAD_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOAD_SIZE")
+            .field("dcache_preload_size", &self.dcache_preload_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.."]
+    #[inline(always)]
+    pub fn dcache_preload_size(&mut self) -> DCACHE_PRELOAD_SIZE_W<DCACHE_PRELOAD_SIZE_SPEC> {
+        DCACHE_PRELOAD_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_preload_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_preload_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOAD_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOAD_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_preload_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOAD_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_preload_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOAD_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOAD_SIZE to value 0"]
+impl crate::Resettable for DCACHE_PRELOAD_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_prelock_ctrl.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `DCACHE_PRELOCK_CTRL` reader"]
+pub type R = crate::R<DCACHE_PRELOCK_CTRL_SPEC>;
+#[doc = "Register `DCACHE_PRELOCK_CTRL` writer"]
+pub type W = crate::W<DCACHE_PRELOCK_CTRL_SPEC>;
+#[doc = "Field `DCACHE_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function."]
+pub type DCACHE_PRELOCK_SCT0_EN_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function."]
+pub type DCACHE_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function."]
+pub type DCACHE_PRELOCK_SCT1_EN_R = crate::BitReader;
+#[doc = "Field `DCACHE_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function."]
+pub type DCACHE_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
+    #[inline(always)]
+    pub fn dcache_prelock_sct0_en(&self) -> DCACHE_PRELOCK_SCT0_EN_R {
+        DCACHE_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
+    #[inline(always)]
+    pub fn dcache_prelock_sct1_en(&self) -> DCACHE_PRELOCK_SCT1_EN_R {
+        DCACHE_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOCK_CTRL")
+            .field("dcache_prelock_sct0_en", &self.dcache_prelock_sct0_en())
+            .field("dcache_prelock_sct1_en", &self.dcache_prelock_sct1_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
+    #[inline(always)]
+    pub fn dcache_prelock_sct0_en(&mut self) -> DCACHE_PRELOCK_SCT0_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
+        DCACHE_PRELOCK_SCT0_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
+    #[inline(always)]
+    pub fn dcache_prelock_sct1_en(&mut self) -> DCACHE_PRELOCK_SCT1_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
+        DCACHE_PRELOCK_SCT1_EN_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOCK_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOCK_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_prelock_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOCK_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_prelock_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOCK_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOCK_CTRL to value 0"]
+impl crate::Resettable for DCACHE_PRELOCK_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `DCACHE_PRELOCK_SCT0_ADDR` reader"]
+pub type R = crate::R<DCACHE_PRELOCK_SCT0_ADDR_SPEC>;
+#[doc = "Register `DCACHE_PRELOCK_SCT0_ADDR` writer"]
+pub type W = crate::W<DCACHE_PRELOCK_SCT0_ADDR_SPEC>;
+#[doc = "Field `DCACHE_PRELOCK_SCT0_ADDR` reader - The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG"]
+pub type DCACHE_PRELOCK_SCT0_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_PRELOCK_SCT0_ADDR` writer - The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG"]
+pub type DCACHE_PRELOCK_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct0_addr(&self) -> DCACHE_PRELOCK_SCT0_ADDR_R {
+        DCACHE_PRELOCK_SCT0_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOCK_SCT0_ADDR")
+            .field("dcache_prelock_sct0_addr", &self.dcache_prelock_sct0_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct0_addr(
+        &mut self,
+    ) -> DCACHE_PRELOCK_SCT0_ADDR_W<DCACHE_PRELOCK_SCT0_ADDR_SPEC> {
+        DCACHE_PRELOCK_SCT0_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_sct0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_sct0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOCK_SCT0_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOCK_SCT0_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_prelock_sct0_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOCK_SCT0_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_prelock_sct0_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOCK_SCT0_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOCK_SCT0_ADDR to value 0"]
+impl crate::Resettable for DCACHE_PRELOCK_SCT0_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `DCACHE_PRELOCK_SCT1_ADDR` reader"]
+pub type R = crate::R<DCACHE_PRELOCK_SCT1_ADDR_SPEC>;
+#[doc = "Register `DCACHE_PRELOCK_SCT1_ADDR` writer"]
+pub type W = crate::W<DCACHE_PRELOCK_SCT1_ADDR_SPEC>;
+#[doc = "Field `DCACHE_PRELOCK_SCT1_ADDR` reader - The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG"]
+pub type DCACHE_PRELOCK_SCT1_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_PRELOCK_SCT1_ADDR` writer - The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG"]
+pub type DCACHE_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct1_addr(&self) -> DCACHE_PRELOCK_SCT1_ADDR_R {
+        DCACHE_PRELOCK_SCT1_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOCK_SCT1_ADDR")
+            .field("dcache_prelock_sct1_addr", &self.dcache_prelock_sct1_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct1_addr(
+        &mut self,
+    ) -> DCACHE_PRELOCK_SCT1_ADDR_W<DCACHE_PRELOCK_SCT1_ADDR_SPEC> {
+        DCACHE_PRELOCK_SCT1_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_sct1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_sct1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOCK_SCT1_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOCK_SCT1_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_prelock_sct1_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOCK_SCT1_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_prelock_sct1_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOCK_SCT1_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOCK_SCT1_ADDR to value 0"]
+impl crate::Resettable for DCACHE_PRELOCK_SCT1_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_prelock_sct_size.rs

@@ -0,0 +1,66 @@
+#[doc = "Register `DCACHE_PRELOCK_SCT_SIZE` reader"]
+pub type R = crate::R<DCACHE_PRELOCK_SCT_SIZE_SPEC>;
+#[doc = "Register `DCACHE_PRELOCK_SCT_SIZE` writer"]
+pub type W = crate::W<DCACHE_PRELOCK_SCT_SIZE_SPEC>;
+#[doc = "Field `DCACHE_PRELOCK_SCT1_SIZE` reader - The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG"]
+pub type DCACHE_PRELOCK_SCT1_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `DCACHE_PRELOCK_SCT1_SIZE` writer - The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG"]
+pub type DCACHE_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `DCACHE_PRELOCK_SCT0_SIZE` reader - The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG"]
+pub type DCACHE_PRELOCK_SCT0_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `DCACHE_PRELOCK_SCT0_SIZE` writer - The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG"]
+pub type DCACHE_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct1_size(&self) -> DCACHE_PRELOCK_SCT1_SIZE_R {
+        DCACHE_PRELOCK_SCT1_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct0_size(&self) -> DCACHE_PRELOCK_SCT0_SIZE_R {
+        DCACHE_PRELOCK_SCT0_SIZE_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_PRELOCK_SCT_SIZE")
+            .field("dcache_prelock_sct1_size", &self.dcache_prelock_sct1_size())
+            .field("dcache_prelock_sct0_size", &self.dcache_prelock_sct0_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct1_size(
+        &mut self,
+    ) -> DCACHE_PRELOCK_SCT1_SIZE_W<DCACHE_PRELOCK_SCT_SIZE_SPEC> {
+        DCACHE_PRELOCK_SCT1_SIZE_W::new(self, 0)
+    }
+    #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG"]
+    #[inline(always)]
+    pub fn dcache_prelock_sct0_size(
+        &mut self,
+    ) -> DCACHE_PRELOCK_SCT0_SIZE_W<DCACHE_PRELOCK_SCT_SIZE_SPEC> {
+        DCACHE_PRELOCK_SCT0_SIZE_W::new(self, 16)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_sct_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_sct_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_PRELOCK_SCT_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_PRELOCK_SCT_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_prelock_sct_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_PRELOCK_SCT_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_prelock_sct_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_PRELOCK_SCT_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_PRELOCK_SCT_SIZE to value 0"]
+impl crate::Resettable for DCACHE_PRELOCK_SCT_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_sync_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_SYNC_ADDR` reader"]
+pub type R = crate::R<DCACHE_SYNC_ADDR_SPEC>;
+#[doc = "Register `DCACHE_SYNC_ADDR` writer"]
+pub type W = crate::W<DCACHE_SYNC_ADDR_SPEC>;
+#[doc = "Field `DCACHE_SYNC_ADDR` reader - The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG."]
+pub type DCACHE_SYNC_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_SYNC_ADDR` writer - The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG."]
+pub type DCACHE_SYNC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_sync_addr(&self) -> DCACHE_SYNC_ADDR_R {
+        DCACHE_SYNC_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_SYNC_ADDR")
+            .field("dcache_sync_addr", &self.dcache_sync_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG."]
+    #[inline(always)]
+    pub fn dcache_sync_addr(&mut self) -> DCACHE_SYNC_ADDR_W<DCACHE_SYNC_ADDR_SPEC> {
+        DCACHE_SYNC_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_SYNC_ADDR_SPEC;
+impl crate::RegisterSpec for DCACHE_SYNC_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_sync_addr::R`](R) reader structure"]
+impl crate::Readable for DCACHE_SYNC_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_sync_addr::W`](W) writer structure"]
+impl crate::Writable for DCACHE_SYNC_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_SYNC_ADDR to value 0"]
+impl crate::Resettable for DCACHE_SYNC_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_sync_ctrl.rs

@@ -0,0 +1,85 @@
+#[doc = "Register `DCACHE_SYNC_CTRL` reader"]
+pub type R = crate::R<DCACHE_SYNC_CTRL_SPEC>;
+#[doc = "Register `DCACHE_SYNC_CTRL` writer"]
+pub type W = crate::W<DCACHE_SYNC_CTRL_SPEC>;
+#[doc = "Field `DCACHE_INVALIDATE_ENA` reader - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+pub type DCACHE_INVALIDATE_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_INVALIDATE_ENA` writer - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+pub type DCACHE_INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_WRITEBACK_ENA` reader - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
+pub type DCACHE_WRITEBACK_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_WRITEBACK_ENA` writer - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
+pub type DCACHE_WRITEBACK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_CLEAN_ENA` reader - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
+pub type DCACHE_CLEAN_ENA_R = crate::BitReader;
+#[doc = "Field `DCACHE_CLEAN_ENA` writer - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
+pub type DCACHE_CLEAN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_SYNC_DONE` reader - The bit is used to indicate clean/writeback/invalidate operation is finished."]
+pub type DCACHE_SYNC_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+    #[inline(always)]
+    pub fn dcache_invalidate_ena(&self) -> DCACHE_INVALIDATE_ENA_R {
+        DCACHE_INVALIDATE_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
+    #[inline(always)]
+    pub fn dcache_writeback_ena(&self) -> DCACHE_WRITEBACK_ENA_R {
+        DCACHE_WRITEBACK_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
+    #[inline(always)]
+    pub fn dcache_clean_ena(&self) -> DCACHE_CLEAN_ENA_R {
+        DCACHE_CLEAN_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate clean/writeback/invalidate operation is finished."]
+    #[inline(always)]
+    pub fn dcache_sync_done(&self) -> DCACHE_SYNC_DONE_R {
+        DCACHE_SYNC_DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_SYNC_CTRL")
+            .field("dcache_invalidate_ena", &self.dcache_invalidate_ena())
+            .field("dcache_writeback_ena", &self.dcache_writeback_ena())
+            .field("dcache_clean_ena", &self.dcache_clean_ena())
+            .field("dcache_sync_done", &self.dcache_sync_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+    #[inline(always)]
+    pub fn dcache_invalidate_ena(&mut self) -> DCACHE_INVALIDATE_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
+        DCACHE_INVALIDATE_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
+    #[inline(always)]
+    pub fn dcache_writeback_ena(&mut self) -> DCACHE_WRITEBACK_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
+        DCACHE_WRITEBACK_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
+    #[inline(always)]
+    pub fn dcache_clean_ena(&mut self) -> DCACHE_CLEAN_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
+        DCACHE_CLEAN_ENA_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_SYNC_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_SYNC_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_sync_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_SYNC_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_sync_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_SYNC_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_SYNC_CTRL to value 0x01"]
+impl crate::Resettable for DCACHE_SYNC_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/extmem/dcache_sync_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DCACHE_SYNC_SIZE` reader"]
+pub type R = crate::R<DCACHE_SYNC_SIZE_SPEC>;
+#[doc = "Register `DCACHE_SYNC_SIZE` writer"]
+pub type W = crate::W<DCACHE_SYNC_SIZE_SPEC>;
+#[doc = "Field `DCACHE_SYNC_SIZE` reader - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG."]
+pub type DCACHE_SYNC_SIZE_R = crate::FieldReader<u32>;
+#[doc = "Field `DCACHE_SYNC_SIZE` writer - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG."]
+pub type DCACHE_SYNC_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
+impl R {
+    #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG."]
+    #[inline(always)]
+    pub fn dcache_sync_size(&self) -> DCACHE_SYNC_SIZE_R {
+        DCACHE_SYNC_SIZE_R::new(self.bits & 0x007f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_SYNC_SIZE")
+            .field("dcache_sync_size", &self.dcache_sync_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG."]
+    #[inline(always)]
+    pub fn dcache_sync_size(&mut self) -> DCACHE_SYNC_SIZE_W<DCACHE_SYNC_SIZE_SPEC> {
+        DCACHE_SYNC_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_SYNC_SIZE_SPEC;
+impl crate::RegisterSpec for DCACHE_SYNC_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_sync_size::R`](R) reader structure"]
+impl crate::Readable for DCACHE_SYNC_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_sync_size::W`](W) writer structure"]
+impl crate::Writable for DCACHE_SYNC_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_SYNC_SIZE to value 0"]
+impl crate::Resettable for DCACHE_SYNC_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/dcache_tag_power_ctrl.rs

@@ -0,0 +1,83 @@
+#[doc = "Register `DCACHE_TAG_POWER_CTRL` reader"]
+pub type R = crate::R<DCACHE_TAG_POWER_CTRL_SPEC>;
+#[doc = "Register `DCACHE_TAG_POWER_CTRL` writer"]
+pub type W = crate::W<DCACHE_TAG_POWER_CTRL_SPEC>;
+#[doc = "Field `DCACHE_TAG_MEM_FORCE_ON` reader - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
+pub type DCACHE_TAG_MEM_FORCE_ON_R = crate::BitReader;
+#[doc = "Field `DCACHE_TAG_MEM_FORCE_ON` writer - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
+pub type DCACHE_TAG_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_TAG_MEM_FORCE_PD` reader - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down"]
+pub type DCACHE_TAG_MEM_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `DCACHE_TAG_MEM_FORCE_PD` writer - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down"]
+pub type DCACHE_TAG_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DCACHE_TAG_MEM_FORCE_PU` reader - The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up"]
+pub type DCACHE_TAG_MEM_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `DCACHE_TAG_MEM_FORCE_PU` writer - The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up"]
+pub type DCACHE_TAG_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn dcache_tag_mem_force_on(&self) -> DCACHE_TAG_MEM_FORCE_ON_R {
+        DCACHE_TAG_MEM_FORCE_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down"]
+    #[inline(always)]
+    pub fn dcache_tag_mem_force_pd(&self) -> DCACHE_TAG_MEM_FORCE_PD_R {
+        DCACHE_TAG_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up"]
+    #[inline(always)]
+    pub fn dcache_tag_mem_force_pu(&self) -> DCACHE_TAG_MEM_FORCE_PU_R {
+        DCACHE_TAG_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DCACHE_TAG_POWER_CTRL")
+            .field("dcache_tag_mem_force_on", &self.dcache_tag_mem_force_on())
+            .field("dcache_tag_mem_force_pd", &self.dcache_tag_mem_force_pd())
+            .field("dcache_tag_mem_force_pu", &self.dcache_tag_mem_force_pu())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn dcache_tag_mem_force_on(
+        &mut self,
+    ) -> DCACHE_TAG_MEM_FORCE_ON_W<DCACHE_TAG_POWER_CTRL_SPEC> {
+        DCACHE_TAG_MEM_FORCE_ON_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down"]
+    #[inline(always)]
+    pub fn dcache_tag_mem_force_pd(
+        &mut self,
+    ) -> DCACHE_TAG_MEM_FORCE_PD_W<DCACHE_TAG_POWER_CTRL_SPEC> {
+        DCACHE_TAG_MEM_FORCE_PD_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up"]
+    #[inline(always)]
+    pub fn dcache_tag_mem_force_pu(
+        &mut self,
+    ) -> DCACHE_TAG_MEM_FORCE_PU_W<DCACHE_TAG_POWER_CTRL_SPEC> {
+        DCACHE_TAG_MEM_FORCE_PU_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_tag_power_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_tag_power_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DCACHE_TAG_POWER_CTRL_SPEC;
+impl crate::RegisterSpec for DCACHE_TAG_POWER_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dcache_tag_power_ctrl::R`](R) reader structure"]
+impl crate::Readable for DCACHE_TAG_POWER_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dcache_tag_power_ctrl::W`](W) writer structure"]
+impl crate::Writable for DCACHE_TAG_POWER_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DCACHE_TAG_POWER_CTRL to value 0x05"]
+impl crate::Resettable for DCACHE_TAG_POWER_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x05;
+}

vendor/esp32s3/src/extmem/ibus_acs_cnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IBUS_ACS_CNT` reader"]
+pub type R = crate::R<IBUS_ACS_CNT_SPEC>;
+#[doc = "Field `IBUS_ACS_CNT` reader - The bits are used to count the number of ibus access flash/spiram through icache."]
+pub type IBUS_ACS_CNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to count the number of ibus access flash/spiram through icache."]
+    #[inline(always)]
+    pub fn ibus_acs_cnt(&self) -> IBUS_ACS_CNT_R {
+        IBUS_ACS_CNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IBUS_ACS_CNT")
+            .field("ibus_acs_cnt", &self.ibus_acs_cnt())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_acs_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IBUS_ACS_CNT_SPEC;
+impl crate::RegisterSpec for IBUS_ACS_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ibus_acs_cnt::R`](R) reader structure"]
+impl crate::Readable for IBUS_ACS_CNT_SPEC {}
+#[doc = "`reset()` method sets IBUS_ACS_CNT to value 0"]
+impl crate::Resettable for IBUS_ACS_CNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/ibus_acs_miss_cnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IBUS_ACS_MISS_CNT` reader"]
+pub type R = crate::R<IBUS_ACS_MISS_CNT_SPEC>;
+#[doc = "Field `IBUS_ACS_MISS_CNT` reader - The bits are used to count the number of the cache miss caused by ibus access flash/spiram."]
+pub type IBUS_ACS_MISS_CNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to count the number of the cache miss caused by ibus access flash/spiram."]
+    #[inline(always)]
+    pub fn ibus_acs_miss_cnt(&self) -> IBUS_ACS_MISS_CNT_R {
+        IBUS_ACS_MISS_CNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IBUS_ACS_MISS_CNT")
+            .field("ibus_acs_miss_cnt", &self.ibus_acs_miss_cnt())
+            .finish()
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IBUS_ACS_MISS_CNT_SPEC;
+impl crate::RegisterSpec for IBUS_ACS_MISS_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ibus_acs_miss_cnt::R`](R) reader structure"]
+impl crate::Readable for IBUS_ACS_MISS_CNT_SPEC {}
+#[doc = "`reset()` method sets IBUS_ACS_MISS_CNT to value 0"]
+impl crate::Resettable for IBUS_ACS_MISS_CNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `IBUS_TO_FLASH_END_VADDR` reader"]
+pub type R = crate::R<IBUS_TO_FLASH_END_VADDR_SPEC>;
+#[doc = "Register `IBUS_TO_FLASH_END_VADDR` writer"]
+pub type W = crate::W<IBUS_TO_FLASH_END_VADDR_SPEC>;
+#[doc = "Field `IBUS_TO_FLASH_END_VADDR` reader - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+pub type IBUS_TO_FLASH_END_VADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `IBUS_TO_FLASH_END_VADDR` writer - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+pub type IBUS_TO_FLASH_END_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+    #[inline(always)]
+    pub fn ibus_to_flash_end_vaddr(&self) -> IBUS_TO_FLASH_END_VADDR_R {
+        IBUS_TO_FLASH_END_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IBUS_TO_FLASH_END_VADDR")
+            .field("ibus_to_flash_end_vaddr", &self.ibus_to_flash_end_vaddr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+    #[inline(always)]
+    pub fn ibus_to_flash_end_vaddr(
+        &mut self,
+    ) -> IBUS_TO_FLASH_END_VADDR_W<IBUS_TO_FLASH_END_VADDR_SPEC> {
+        IBUS_TO_FLASH_END_VADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_to_flash_end_vaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibus_to_flash_end_vaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IBUS_TO_FLASH_END_VADDR_SPEC;
+impl crate::RegisterSpec for IBUS_TO_FLASH_END_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ibus_to_flash_end_vaddr::R`](R) reader structure"]
+impl crate::Readable for IBUS_TO_FLASH_END_VADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ibus_to_flash_end_vaddr::W`](W) writer structure"]
+impl crate::Writable for IBUS_TO_FLASH_END_VADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IBUS_TO_FLASH_END_VADDR to value 0x47ff_ffff"]
+impl crate::Resettable for IBUS_TO_FLASH_END_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0x47ff_ffff;
+}

vendor/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `IBUS_TO_FLASH_START_VADDR` reader"]
+pub type R = crate::R<IBUS_TO_FLASH_START_VADDR_SPEC>;
+#[doc = "Register `IBUS_TO_FLASH_START_VADDR` writer"]
+pub type W = crate::W<IBUS_TO_FLASH_START_VADDR_SPEC>;
+#[doc = "Field `IBUS_TO_FLASH_START_VADDR` reader - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+pub type IBUS_TO_FLASH_START_VADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `IBUS_TO_FLASH_START_VADDR` writer - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+pub type IBUS_TO_FLASH_START_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+    #[inline(always)]
+    pub fn ibus_to_flash_start_vaddr(&self) -> IBUS_TO_FLASH_START_VADDR_R {
+        IBUS_TO_FLASH_START_VADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IBUS_TO_FLASH_START_VADDR")
+            .field(
+                "ibus_to_flash_start_vaddr",
+                &self.ibus_to_flash_start_vaddr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
+    #[inline(always)]
+    pub fn ibus_to_flash_start_vaddr(
+        &mut self,
+    ) -> IBUS_TO_FLASH_START_VADDR_W<IBUS_TO_FLASH_START_VADDR_SPEC> {
+        IBUS_TO_FLASH_START_VADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_to_flash_start_vaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibus_to_flash_start_vaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IBUS_TO_FLASH_START_VADDR_SPEC;
+impl crate::RegisterSpec for IBUS_TO_FLASH_START_VADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ibus_to_flash_start_vaddr::R`](R) reader structure"]
+impl crate::Readable for IBUS_TO_FLASH_START_VADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ibus_to_flash_start_vaddr::W`](W) writer structure"]
+impl crate::Writable for IBUS_TO_FLASH_START_VADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IBUS_TO_FLASH_START_VADDR to value 0x4400_0000"]
+impl crate::Resettable for IBUS_TO_FLASH_START_VADDR_SPEC {
+    const RESET_VALUE: u32 = 0x4400_0000;
+}

vendor/esp32s3/src/extmem/icache_atomic_operate_ena.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `ICACHE_ATOMIC_OPERATE_ENA` reader"]
+pub type R = crate::R<ICACHE_ATOMIC_OPERATE_ENA_SPEC>;
+#[doc = "Register `ICACHE_ATOMIC_OPERATE_ENA` writer"]
+pub type W = crate::W<ICACHE_ATOMIC_OPERATE_ENA_SPEC>;
+#[doc = "Field `ICACHE_ATOMIC_OPERATE_ENA` reader - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+pub type ICACHE_ATOMIC_OPERATE_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_ATOMIC_OPERATE_ENA` writer - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+pub type ICACHE_ATOMIC_OPERATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+    #[inline(always)]
+    pub fn icache_atomic_operate_ena(&self) -> ICACHE_ATOMIC_OPERATE_ENA_R {
+        ICACHE_ATOMIC_OPERATE_ENA_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_ATOMIC_OPERATE_ENA")
+            .field(
+                "icache_atomic_operate_ena",
+                &self.icache_atomic_operate_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
+    #[inline(always)]
+    pub fn icache_atomic_operate_ena(
+        &mut self,
+    ) -> ICACHE_ATOMIC_OPERATE_ENA_W<ICACHE_ATOMIC_OPERATE_ENA_SPEC> {
+        ICACHE_ATOMIC_OPERATE_ENA_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_atomic_operate_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_atomic_operate_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_ATOMIC_OPERATE_ENA_SPEC;
+impl crate::RegisterSpec for ICACHE_ATOMIC_OPERATE_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_atomic_operate_ena::R`](R) reader structure"]
+impl crate::Readable for ICACHE_ATOMIC_OPERATE_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_atomic_operate_ena::W`](W) writer structure"]
+impl crate::Writable for ICACHE_ATOMIC_OPERATE_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_ATOMIC_OPERATE_ENA to value 0x01"]
+impl crate::Resettable for ICACHE_ATOMIC_OPERATE_ENA_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/extmem/icache_autoload_ctrl.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `ICACHE_AUTOLOAD_CTRL` reader"]
+pub type R = crate::R<ICACHE_AUTOLOAD_CTRL_SPEC>;
+#[doc = "Register `ICACHE_AUTOLOAD_CTRL` writer"]
+pub type W = crate::W<ICACHE_AUTOLOAD_CTRL_SPEC>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT0_ENA` reader - The bits are used to enable the first section for autoload operation."]
+pub type ICACHE_AUTOLOAD_SCT0_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT0_ENA` writer - The bits are used to enable the first section for autoload operation."]
+pub type ICACHE_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT1_ENA` reader - The bits are used to enable the second section for autoload operation."]
+pub type ICACHE_AUTOLOAD_SCT1_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT1_ENA` writer - The bits are used to enable the second section for autoload operation."]
+pub type ICACHE_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable."]
+pub type ICACHE_AUTOLOAD_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_AUTOLOAD_ENA` writer - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable."]
+pub type ICACHE_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_AUTOLOAD_DONE` reader - The bit is used to indicate autoload operation is finished."]
+pub type ICACHE_AUTOLOAD_DONE_R = crate::BitReader;
+#[doc = "Field `ICACHE_AUTOLOAD_ORDER` reader - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+pub type ICACHE_AUTOLOAD_ORDER_R = crate::BitReader;
+#[doc = "Field `ICACHE_AUTOLOAD_ORDER` writer - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+pub type ICACHE_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_AUTOLOAD_RQST` reader - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+pub type ICACHE_AUTOLOAD_RQST_R = crate::FieldReader;
+#[doc = "Field `ICACHE_AUTOLOAD_RQST` writer - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+pub type ICACHE_AUTOLOAD_RQST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `ICACHE_AUTOLOAD_SIZE` reader - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+pub type ICACHE_AUTOLOAD_SIZE_R = crate::FieldReader;
+#[doc = "Field `ICACHE_AUTOLOAD_SIZE` writer - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+pub type ICACHE_AUTOLOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `ICACHE_AUTOLOAD_BUFFER_CLEAR` reader - The bit is used to clear autoload buffer in icache."]
+pub type ICACHE_AUTOLOAD_BUFFER_CLEAR_R = crate::BitReader;
+#[doc = "Field `ICACHE_AUTOLOAD_BUFFER_CLEAR` writer - The bit is used to clear autoload buffer in icache."]
+pub type ICACHE_AUTOLOAD_BUFFER_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
+    #[inline(always)]
+    pub fn icache_autoload_sct0_ena(&self) -> ICACHE_AUTOLOAD_SCT0_ENA_R {
+        ICACHE_AUTOLOAD_SCT0_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bits are used to enable the second section for autoload operation."]
+    #[inline(always)]
+    pub fn icache_autoload_sct1_ena(&self) -> ICACHE_AUTOLOAD_SCT1_ENA_R {
+        ICACHE_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable."]
+    #[inline(always)]
+    pub fn icache_autoload_ena(&self) -> ICACHE_AUTOLOAD_ENA_R {
+        ICACHE_AUTOLOAD_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to indicate autoload operation is finished."]
+    #[inline(always)]
+    pub fn icache_autoload_done(&self) -> ICACHE_AUTOLOAD_DONE_R {
+        ICACHE_AUTOLOAD_DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn icache_autoload_order(&self) -> ICACHE_AUTOLOAD_ORDER_R {
+        ICACHE_AUTOLOAD_ORDER_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+    #[inline(always)]
+    pub fn icache_autoload_rqst(&self) -> ICACHE_AUTOLOAD_RQST_R {
+        ICACHE_AUTOLOAD_RQST_R::new(((self.bits >> 5) & 3) as u8)
+    }
+    #[doc = "Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+    #[inline(always)]
+    pub fn icache_autoload_size(&self) -> ICACHE_AUTOLOAD_SIZE_R {
+        ICACHE_AUTOLOAD_SIZE_R::new(((self.bits >> 7) & 3) as u8)
+    }
+    #[doc = "Bit 9 - The bit is used to clear autoload buffer in icache."]
+    #[inline(always)]
+    pub fn icache_autoload_buffer_clear(&self) -> ICACHE_AUTOLOAD_BUFFER_CLEAR_R {
+        ICACHE_AUTOLOAD_BUFFER_CLEAR_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_AUTOLOAD_CTRL")
+            .field("icache_autoload_sct0_ena", &self.icache_autoload_sct0_ena())
+            .field("icache_autoload_sct1_ena", &self.icache_autoload_sct1_ena())
+            .field("icache_autoload_ena", &self.icache_autoload_ena())
+            .field("icache_autoload_done", &self.icache_autoload_done())
+            .field("icache_autoload_order", &self.icache_autoload_order())
+            .field("icache_autoload_rqst", &self.icache_autoload_rqst())
+            .field("icache_autoload_size", &self.icache_autoload_size())
+            .field(
+                "icache_autoload_buffer_clear",
+                &self.icache_autoload_buffer_clear(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
+    #[inline(always)]
+    pub fn icache_autoload_sct0_ena(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_SCT0_ENA_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_SCT0_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bits are used to enable the second section for autoload operation."]
+    #[inline(always)]
+    pub fn icache_autoload_sct1_ena(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_SCT1_ENA_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_SCT1_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable."]
+    #[inline(always)]
+    pub fn icache_autoload_ena(&mut self) -> ICACHE_AUTOLOAD_ENA_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn icache_autoload_order(&mut self) -> ICACHE_AUTOLOAD_ORDER_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_ORDER_W::new(self, 4)
+    }
+    #[doc = "Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
+    #[inline(always)]
+    pub fn icache_autoload_rqst(&mut self) -> ICACHE_AUTOLOAD_RQST_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_RQST_W::new(self, 5)
+    }
+    #[doc = "Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
+    #[inline(always)]
+    pub fn icache_autoload_size(&mut self) -> ICACHE_AUTOLOAD_SIZE_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_SIZE_W::new(self, 7)
+    }
+    #[doc = "Bit 9 - The bit is used to clear autoload buffer in icache."]
+    #[inline(always)]
+    pub fn icache_autoload_buffer_clear(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_BUFFER_CLEAR_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
+        ICACHE_AUTOLOAD_BUFFER_CLEAR_W::new(self, 9)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_AUTOLOAD_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_AUTOLOAD_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_autoload_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_AUTOLOAD_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_autoload_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_AUTOLOAD_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_AUTOLOAD_CTRL to value 0x08"]
+impl crate::Resettable for ICACHE_AUTOLOAD_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x08;
+}

vendor/esp32s3/src/extmem/icache_autoload_sct0_addr.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `ICACHE_AUTOLOAD_SCT0_ADDR` reader"]
+pub type R = crate::R<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
+#[doc = "Register `ICACHE_AUTOLOAD_SCT0_ADDR` writer"]
+pub type W = crate::W<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT0_ADDR` reader - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+pub type ICACHE_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT0_ADDR` writer - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+pub type ICACHE_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct0_addr(&self) -> ICACHE_AUTOLOAD_SCT0_ADDR_R {
+        ICACHE_AUTOLOAD_SCT0_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_AUTOLOAD_SCT0_ADDR")
+            .field(
+                "icache_autoload_sct0_addr",
+                &self.icache_autoload_sct0_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct0_addr(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_SCT0_ADDR_W<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
+        ICACHE_AUTOLOAD_SCT0_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_AUTOLOAD_SCT0_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_autoload_sct0_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_autoload_sct0_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_AUTOLOAD_SCT0_ADDR to value 0"]
+impl crate::Resettable for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_autoload_sct0_size.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `ICACHE_AUTOLOAD_SCT0_SIZE` reader"]
+pub type R = crate::R<ICACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
+#[doc = "Register `ICACHE_AUTOLOAD_SCT0_SIZE` writer"]
+pub type W = crate::W<ICACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT0_SIZE` reader - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+pub type ICACHE_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT0_SIZE` writer - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+pub type ICACHE_AUTOLOAD_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
+impl R {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct0_size(&self) -> ICACHE_AUTOLOAD_SCT0_SIZE_R {
+        ICACHE_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x07ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_AUTOLOAD_SCT0_SIZE")
+            .field(
+                "icache_autoload_sct0_size",
+                &self.icache_autoload_sct0_size(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct0_size(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_SCT0_SIZE_W<ICACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
+        ICACHE_AUTOLOAD_SCT0_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct0_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct0_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_AUTOLOAD_SCT0_SIZE_SPEC;
+impl crate::RegisterSpec for ICACHE_AUTOLOAD_SCT0_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_autoload_sct0_size::R`](R) reader structure"]
+impl crate::Readable for ICACHE_AUTOLOAD_SCT0_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_autoload_sct0_size::W`](W) writer structure"]
+impl crate::Writable for ICACHE_AUTOLOAD_SCT0_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_AUTOLOAD_SCT0_SIZE to value 0"]
+impl crate::Resettable for ICACHE_AUTOLOAD_SCT0_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_autoload_sct1_addr.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `ICACHE_AUTOLOAD_SCT1_ADDR` reader"]
+pub type R = crate::R<ICACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
+#[doc = "Register `ICACHE_AUTOLOAD_SCT1_ADDR` writer"]
+pub type W = crate::W<ICACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT1_ADDR` reader - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+pub type ICACHE_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT1_ADDR` writer - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+pub type ICACHE_AUTOLOAD_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct1_addr(&self) -> ICACHE_AUTOLOAD_SCT1_ADDR_R {
+        ICACHE_AUTOLOAD_SCT1_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_AUTOLOAD_SCT1_ADDR")
+            .field(
+                "icache_autoload_sct1_addr",
+                &self.icache_autoload_sct1_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct1_addr(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_SCT1_ADDR_W<ICACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
+        ICACHE_AUTOLOAD_SCT1_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_AUTOLOAD_SCT1_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_AUTOLOAD_SCT1_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_autoload_sct1_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_AUTOLOAD_SCT1_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_autoload_sct1_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_AUTOLOAD_SCT1_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_AUTOLOAD_SCT1_ADDR to value 0"]
+impl crate::Resettable for ICACHE_AUTOLOAD_SCT1_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_autoload_sct1_size.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `ICACHE_AUTOLOAD_SCT1_SIZE` reader"]
+pub type R = crate::R<ICACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
+#[doc = "Register `ICACHE_AUTOLOAD_SCT1_SIZE` writer"]
+pub type W = crate::W<ICACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT1_SIZE` reader - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+pub type ICACHE_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_AUTOLOAD_SCT1_SIZE` writer - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+pub type ICACHE_AUTOLOAD_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
+impl R {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct1_size(&self) -> ICACHE_AUTOLOAD_SCT1_SIZE_R {
+        ICACHE_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x07ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_AUTOLOAD_SCT1_SIZE")
+            .field(
+                "icache_autoload_sct1_size",
+                &self.icache_autoload_sct1_size(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
+    #[inline(always)]
+    pub fn icache_autoload_sct1_size(
+        &mut self,
+    ) -> ICACHE_AUTOLOAD_SCT1_SIZE_W<ICACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
+        ICACHE_AUTOLOAD_SCT1_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct1_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct1_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_AUTOLOAD_SCT1_SIZE_SPEC;
+impl crate::RegisterSpec for ICACHE_AUTOLOAD_SCT1_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_autoload_sct1_size::R`](R) reader structure"]
+impl crate::Readable for ICACHE_AUTOLOAD_SCT1_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_autoload_sct1_size::W`](W) writer structure"]
+impl crate::Writable for ICACHE_AUTOLOAD_SCT1_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_AUTOLOAD_SCT1_SIZE to value 0"]
+impl crate::Resettable for ICACHE_AUTOLOAD_SCT1_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_ctrl.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `ICACHE_CTRL` reader"]
+pub type R = crate::R<ICACHE_CTRL_SPEC>;
+#[doc = "Register `ICACHE_CTRL` writer"]
+pub type W = crate::W<ICACHE_CTRL_SPEC>;
+#[doc = "Field `ICACHE_ENABLE` reader - The bit is used to activate the data cache. 0: disable, 1: enable"]
+pub type ICACHE_ENABLE_R = crate::BitReader;
+#[doc = "Field `ICACHE_ENABLE` writer - The bit is used to activate the data cache. 0: disable, 1: enable"]
+pub type ICACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_WAY_MODE` reader - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
+pub type ICACHE_WAY_MODE_R = crate::BitReader;
+#[doc = "Field `ICACHE_WAY_MODE` writer - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
+pub type ICACHE_WAY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_SIZE_MODE` reader - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
+pub type ICACHE_SIZE_MODE_R = crate::BitReader;
+#[doc = "Field `ICACHE_SIZE_MODE` writer - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
+pub type ICACHE_SIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_BLOCKSIZE_MODE` reader - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
+pub type ICACHE_BLOCKSIZE_MODE_R = crate::BitReader;
+#[doc = "Field `ICACHE_BLOCKSIZE_MODE` writer - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
+pub type ICACHE_BLOCKSIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn icache_enable(&self) -> ICACHE_ENABLE_R {
+        ICACHE_ENABLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
+    #[inline(always)]
+    pub fn icache_way_mode(&self) -> ICACHE_WAY_MODE_R {
+        ICACHE_WAY_MODE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
+    #[inline(always)]
+    pub fn icache_size_mode(&self) -> ICACHE_SIZE_MODE_R {
+        ICACHE_SIZE_MODE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
+    #[inline(always)]
+    pub fn icache_blocksize_mode(&self) -> ICACHE_BLOCKSIZE_MODE_R {
+        ICACHE_BLOCKSIZE_MODE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_CTRL")
+            .field("icache_enable", &self.icache_enable())
+            .field("icache_way_mode", &self.icache_way_mode())
+            .field("icache_size_mode", &self.icache_size_mode())
+            .field("icache_blocksize_mode", &self.icache_blocksize_mode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn icache_enable(&mut self) -> ICACHE_ENABLE_W<ICACHE_CTRL_SPEC> {
+        ICACHE_ENABLE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
+    #[inline(always)]
+    pub fn icache_way_mode(&mut self) -> ICACHE_WAY_MODE_W<ICACHE_CTRL_SPEC> {
+        ICACHE_WAY_MODE_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
+    #[inline(always)]
+    pub fn icache_size_mode(&mut self) -> ICACHE_SIZE_MODE_W<ICACHE_CTRL_SPEC> {
+        ICACHE_SIZE_MODE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
+    #[inline(always)]
+    pub fn icache_blocksize_mode(&mut self) -> ICACHE_BLOCKSIZE_MODE_W<ICACHE_CTRL_SPEC> {
+        ICACHE_BLOCKSIZE_MODE_W::new(self, 3)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_CTRL to value 0"]
+impl crate::Resettable for ICACHE_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_ctrl1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `ICACHE_CTRL1` reader"]
+pub type R = crate::R<ICACHE_CTRL1_SPEC>;
+#[doc = "Register `ICACHE_CTRL1` writer"]
+pub type W = crate::W<ICACHE_CTRL1_SPEC>;
+#[doc = "Field `ICACHE_SHUT_CORE0_BUS` reader - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
+pub type ICACHE_SHUT_CORE0_BUS_R = crate::BitReader;
+#[doc = "Field `ICACHE_SHUT_CORE0_BUS` writer - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
+pub type ICACHE_SHUT_CORE0_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_SHUT_CORE1_BUS` reader - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
+pub type ICACHE_SHUT_CORE1_BUS_R = crate::BitReader;
+#[doc = "Field `ICACHE_SHUT_CORE1_BUS` writer - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
+pub type ICACHE_SHUT_CORE1_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn icache_shut_core0_bus(&self) -> ICACHE_SHUT_CORE0_BUS_R {
+        ICACHE_SHUT_CORE0_BUS_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn icache_shut_core1_bus(&self) -> ICACHE_SHUT_CORE1_BUS_R {
+        ICACHE_SHUT_CORE1_BUS_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_CTRL1")
+            .field("icache_shut_core0_bus", &self.icache_shut_core0_bus())
+            .field("icache_shut_core1_bus", &self.icache_shut_core1_bus())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn icache_shut_core0_bus(&mut self) -> ICACHE_SHUT_CORE0_BUS_W<ICACHE_CTRL1_SPEC> {
+        ICACHE_SHUT_CORE0_BUS_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
+    #[inline(always)]
+    pub fn icache_shut_core1_bus(&mut self) -> ICACHE_SHUT_CORE1_BUS_W<ICACHE_CTRL1_SPEC> {
+        ICACHE_SHUT_CORE1_BUS_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_CTRL1_SPEC;
+impl crate::RegisterSpec for ICACHE_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_ctrl1::R`](R) reader structure"]
+impl crate::Readable for ICACHE_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_ctrl1::W`](W) writer structure"]
+impl crate::Writable for ICACHE_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_CTRL1 to value 0x03"]
+impl crate::Resettable for ICACHE_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0x03;
+}

vendor/esp32s3/src/extmem/icache_freeze.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `ICACHE_FREEZE` reader"]
+pub type R = crate::R<ICACHE_FREEZE_SPEC>;
+#[doc = "Register `ICACHE_FREEZE` writer"]
+pub type W = crate::W<ICACHE_FREEZE_SPEC>;
+#[doc = "Field `ENA` reader - The bit is used to enable icache freeze mode"]
+pub type ENA_R = crate::BitReader;
+#[doc = "Field `ENA` writer - The bit is used to enable icache freeze mode"]
+pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MODE` reader - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+pub type MODE_R = crate::BitReader;
+#[doc = "Field `MODE` writer - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DONE` reader - The bit is used to indicate icache freeze success"]
+pub type DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
+    #[inline(always)]
+    pub fn ena(&self) -> ENA_R {
+        ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate icache freeze success"]
+    #[inline(always)]
+    pub fn done(&self) -> DONE_R {
+        DONE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_FREEZE")
+            .field("ena", &self.ena())
+            .field("mode", &self.mode())
+            .field("done", &self.done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
+    #[inline(always)]
+    pub fn ena(&mut self) -> ENA_W<ICACHE_FREEZE_SPEC> {
+        ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<ICACHE_FREEZE_SPEC> {
+        MODE_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_freeze::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_freeze::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_FREEZE_SPEC;
+impl crate::RegisterSpec for ICACHE_FREEZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_freeze::R`](R) reader structure"]
+impl crate::Readable for ICACHE_FREEZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_freeze::W`](W) writer structure"]
+impl crate::Writable for ICACHE_FREEZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_FREEZE to value 0x04"]
+impl crate::Resettable for ICACHE_FREEZE_SPEC {
+    const RESET_VALUE: u32 = 0x04;
+}

vendor/esp32s3/src/extmem/icache_lock_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ICACHE_LOCK_ADDR` reader"]
+pub type R = crate::R<ICACHE_LOCK_ADDR_SPEC>;
+#[doc = "Register `ICACHE_LOCK_ADDR` writer"]
+pub type W = crate::W<ICACHE_LOCK_ADDR_SPEC>;
+#[doc = "Field `ICACHE_LOCK_ADDR` reader - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
+pub type ICACHE_LOCK_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_LOCK_ADDR` writer - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
+pub type ICACHE_LOCK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
+    #[inline(always)]
+    pub fn icache_lock_addr(&self) -> ICACHE_LOCK_ADDR_R {
+        ICACHE_LOCK_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_LOCK_ADDR")
+            .field("icache_lock_addr", &self.icache_lock_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
+    #[inline(always)]
+    pub fn icache_lock_addr(&mut self) -> ICACHE_LOCK_ADDR_W<ICACHE_LOCK_ADDR_SPEC> {
+        ICACHE_LOCK_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_lock_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_lock_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_LOCK_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_LOCK_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_lock_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_LOCK_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_lock_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_LOCK_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_LOCK_ADDR to value 0"]
+impl crate::Resettable for ICACHE_LOCK_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_lock_ctrl.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `ICACHE_LOCK_CTRL` reader"]
+pub type R = crate::R<ICACHE_LOCK_CTRL_SPEC>;
+#[doc = "Register `ICACHE_LOCK_CTRL` writer"]
+pub type W = crate::W<ICACHE_LOCK_CTRL_SPEC>;
+#[doc = "Field `ICACHE_LOCK_ENA` reader - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+pub type ICACHE_LOCK_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_LOCK_ENA` writer - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+pub type ICACHE_LOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_UNLOCK_ENA` reader - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+pub type ICACHE_UNLOCK_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_UNLOCK_ENA` writer - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+pub type ICACHE_UNLOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_LOCK_DONE` reader - The bit is used to indicate unlock/lock operation is finished."]
+pub type ICACHE_LOCK_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+    #[inline(always)]
+    pub fn icache_lock_ena(&self) -> ICACHE_LOCK_ENA_R {
+        ICACHE_LOCK_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+    #[inline(always)]
+    pub fn icache_unlock_ena(&self) -> ICACHE_UNLOCK_ENA_R {
+        ICACHE_UNLOCK_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to indicate unlock/lock operation is finished."]
+    #[inline(always)]
+    pub fn icache_lock_done(&self) -> ICACHE_LOCK_DONE_R {
+        ICACHE_LOCK_DONE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_LOCK_CTRL")
+            .field("icache_lock_ena", &self.icache_lock_ena())
+            .field("icache_unlock_ena", &self.icache_unlock_ena())
+            .field("icache_lock_done", &self.icache_lock_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
+    #[inline(always)]
+    pub fn icache_lock_ena(&mut self) -> ICACHE_LOCK_ENA_W<ICACHE_LOCK_CTRL_SPEC> {
+        ICACHE_LOCK_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
+    #[inline(always)]
+    pub fn icache_unlock_ena(&mut self) -> ICACHE_UNLOCK_ENA_W<ICACHE_LOCK_CTRL_SPEC> {
+        ICACHE_UNLOCK_ENA_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_LOCK_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_LOCK_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_lock_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_LOCK_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_lock_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_LOCK_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_LOCK_CTRL to value 0x04"]
+impl crate::Resettable for ICACHE_LOCK_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x04;
+}

vendor/esp32s3/src/extmem/icache_lock_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ICACHE_LOCK_SIZE` reader"]
+pub type R = crate::R<ICACHE_LOCK_SIZE_SPEC>;
+#[doc = "Register `ICACHE_LOCK_SIZE` writer"]
+pub type W = crate::W<ICACHE_LOCK_SIZE_SPEC>;
+#[doc = "Field `ICACHE_LOCK_SIZE` reader - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
+pub type ICACHE_LOCK_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `ICACHE_LOCK_SIZE` writer - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
+pub type ICACHE_LOCK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
+    #[inline(always)]
+    pub fn icache_lock_size(&self) -> ICACHE_LOCK_SIZE_R {
+        ICACHE_LOCK_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_LOCK_SIZE")
+            .field("icache_lock_size", &self.icache_lock_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
+    #[inline(always)]
+    pub fn icache_lock_size(&mut self) -> ICACHE_LOCK_SIZE_W<ICACHE_LOCK_SIZE_SPEC> {
+        ICACHE_LOCK_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_lock_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_lock_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_LOCK_SIZE_SPEC;
+impl crate::RegisterSpec for ICACHE_LOCK_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_lock_size::R`](R) reader structure"]
+impl crate::Readable for ICACHE_LOCK_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_lock_size::W`](W) writer structure"]
+impl crate::Writable for ICACHE_LOCK_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_LOCK_SIZE to value 0"]
+impl crate::Resettable for ICACHE_LOCK_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_preload_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ICACHE_PRELOAD_ADDR` reader"]
+pub type R = crate::R<ICACHE_PRELOAD_ADDR_SPEC>;
+#[doc = "Register `ICACHE_PRELOAD_ADDR` writer"]
+pub type W = crate::W<ICACHE_PRELOAD_ADDR_SPEC>;
+#[doc = "Field `ICACHE_PRELOAD_ADDR` reader - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
+pub type ICACHE_PRELOAD_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_PRELOAD_ADDR` writer - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
+pub type ICACHE_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
+    #[inline(always)]
+    pub fn icache_preload_addr(&self) -> ICACHE_PRELOAD_ADDR_R {
+        ICACHE_PRELOAD_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOAD_ADDR")
+            .field("icache_preload_addr", &self.icache_preload_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
+    #[inline(always)]
+    pub fn icache_preload_addr(&mut self) -> ICACHE_PRELOAD_ADDR_W<ICACHE_PRELOAD_ADDR_SPEC> {
+        ICACHE_PRELOAD_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_preload_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_preload_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOAD_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOAD_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_preload_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOAD_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_preload_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOAD_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOAD_ADDR to value 0"]
+impl crate::Resettable for ICACHE_PRELOAD_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_preload_ctrl.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `ICACHE_PRELOAD_CTRL` reader"]
+pub type R = crate::R<ICACHE_PRELOAD_CTRL_SPEC>;
+#[doc = "Register `ICACHE_PRELOAD_CTRL` writer"]
+pub type W = crate::W<ICACHE_PRELOAD_CTRL_SPEC>;
+#[doc = "Field `ICACHE_PRELOAD_ENA` reader - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+pub type ICACHE_PRELOAD_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOAD_ENA` writer - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+pub type ICACHE_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_PRELOAD_DONE` reader - The bit is used to indicate preload operation is finished."]
+pub type ICACHE_PRELOAD_DONE_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+pub type ICACHE_PRELOAD_ORDER_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+pub type ICACHE_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+    #[inline(always)]
+    pub fn icache_preload_ena(&self) -> ICACHE_PRELOAD_ENA_R {
+        ICACHE_PRELOAD_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate preload operation is finished."]
+    #[inline(always)]
+    pub fn icache_preload_done(&self) -> ICACHE_PRELOAD_DONE_R {
+        ICACHE_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn icache_preload_order(&self) -> ICACHE_PRELOAD_ORDER_R {
+        ICACHE_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOAD_CTRL")
+            .field("icache_preload_ena", &self.icache_preload_ena())
+            .field("icache_preload_done", &self.icache_preload_done())
+            .field("icache_preload_order", &self.icache_preload_order())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
+    #[inline(always)]
+    pub fn icache_preload_ena(&mut self) -> ICACHE_PRELOAD_ENA_W<ICACHE_PRELOAD_CTRL_SPEC> {
+        ICACHE_PRELOAD_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
+    #[inline(always)]
+    pub fn icache_preload_order(&mut self) -> ICACHE_PRELOAD_ORDER_W<ICACHE_PRELOAD_CTRL_SPEC> {
+        ICACHE_PRELOAD_ORDER_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_preload_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_preload_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOAD_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOAD_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_preload_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOAD_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_preload_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOAD_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOAD_CTRL to value 0x02"]
+impl crate::Resettable for ICACHE_PRELOAD_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x02;
+}

vendor/esp32s3/src/extmem/icache_preload_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ICACHE_PRELOAD_SIZE` reader"]
+pub type R = crate::R<ICACHE_PRELOAD_SIZE_SPEC>;
+#[doc = "Register `ICACHE_PRELOAD_SIZE` writer"]
+pub type W = crate::W<ICACHE_PRELOAD_SIZE_SPEC>;
+#[doc = "Field `ICACHE_PRELOAD_SIZE` reader - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
+pub type ICACHE_PRELOAD_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `ICACHE_PRELOAD_SIZE` writer - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
+pub type ICACHE_PRELOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
+    #[inline(always)]
+    pub fn icache_preload_size(&self) -> ICACHE_PRELOAD_SIZE_R {
+        ICACHE_PRELOAD_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOAD_SIZE")
+            .field("icache_preload_size", &self.icache_preload_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
+    #[inline(always)]
+    pub fn icache_preload_size(&mut self) -> ICACHE_PRELOAD_SIZE_W<ICACHE_PRELOAD_SIZE_SPEC> {
+        ICACHE_PRELOAD_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_preload_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_preload_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOAD_SIZE_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOAD_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_preload_size::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOAD_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_preload_size::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOAD_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOAD_SIZE to value 0"]
+impl crate::Resettable for ICACHE_PRELOAD_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_prelock_ctrl.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `ICACHE_PRELOCK_CTRL` reader"]
+pub type R = crate::R<ICACHE_PRELOCK_CTRL_SPEC>;
+#[doc = "Register `ICACHE_PRELOCK_CTRL` writer"]
+pub type W = crate::W<ICACHE_PRELOCK_CTRL_SPEC>;
+#[doc = "Field `ICACHE_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function."]
+pub type ICACHE_PRELOCK_SCT0_EN_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function."]
+pub type ICACHE_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function."]
+pub type ICACHE_PRELOCK_SCT1_EN_R = crate::BitReader;
+#[doc = "Field `ICACHE_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function."]
+pub type ICACHE_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
+    #[inline(always)]
+    pub fn icache_prelock_sct0_en(&self) -> ICACHE_PRELOCK_SCT0_EN_R {
+        ICACHE_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
+    #[inline(always)]
+    pub fn icache_prelock_sct1_en(&self) -> ICACHE_PRELOCK_SCT1_EN_R {
+        ICACHE_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOCK_CTRL")
+            .field("icache_prelock_sct0_en", &self.icache_prelock_sct0_en())
+            .field("icache_prelock_sct1_en", &self.icache_prelock_sct1_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
+    #[inline(always)]
+    pub fn icache_prelock_sct0_en(&mut self) -> ICACHE_PRELOCK_SCT0_EN_W<ICACHE_PRELOCK_CTRL_SPEC> {
+        ICACHE_PRELOCK_SCT0_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
+    #[inline(always)]
+    pub fn icache_prelock_sct1_en(&mut self) -> ICACHE_PRELOCK_SCT1_EN_W<ICACHE_PRELOCK_CTRL_SPEC> {
+        ICACHE_PRELOCK_SCT1_EN_W::new(self, 1)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOCK_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOCK_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_prelock_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOCK_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_prelock_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOCK_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOCK_CTRL to value 0"]
+impl crate::Resettable for ICACHE_PRELOCK_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_prelock_sct0_addr.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `ICACHE_PRELOCK_SCT0_ADDR` reader"]
+pub type R = crate::R<ICACHE_PRELOCK_SCT0_ADDR_SPEC>;
+#[doc = "Register `ICACHE_PRELOCK_SCT0_ADDR` writer"]
+pub type W = crate::W<ICACHE_PRELOCK_SCT0_ADDR_SPEC>;
+#[doc = "Field `ICACHE_PRELOCK_SCT0_ADDR` reader - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
+pub type ICACHE_PRELOCK_SCT0_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_PRELOCK_SCT0_ADDR` writer - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
+pub type ICACHE_PRELOCK_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct0_addr(&self) -> ICACHE_PRELOCK_SCT0_ADDR_R {
+        ICACHE_PRELOCK_SCT0_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOCK_SCT0_ADDR")
+            .field("icache_prelock_sct0_addr", &self.icache_prelock_sct0_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct0_addr(
+        &mut self,
+    ) -> ICACHE_PRELOCK_SCT0_ADDR_W<ICACHE_PRELOCK_SCT0_ADDR_SPEC> {
+        ICACHE_PRELOCK_SCT0_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOCK_SCT0_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOCK_SCT0_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_prelock_sct0_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOCK_SCT0_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_prelock_sct0_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOCK_SCT0_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOCK_SCT0_ADDR to value 0"]
+impl crate::Resettable for ICACHE_PRELOCK_SCT0_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_prelock_sct1_addr.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `ICACHE_PRELOCK_SCT1_ADDR` reader"]
+pub type R = crate::R<ICACHE_PRELOCK_SCT1_ADDR_SPEC>;
+#[doc = "Register `ICACHE_PRELOCK_SCT1_ADDR` writer"]
+pub type W = crate::W<ICACHE_PRELOCK_SCT1_ADDR_SPEC>;
+#[doc = "Field `ICACHE_PRELOCK_SCT1_ADDR` reader - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
+pub type ICACHE_PRELOCK_SCT1_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_PRELOCK_SCT1_ADDR` writer - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
+pub type ICACHE_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct1_addr(&self) -> ICACHE_PRELOCK_SCT1_ADDR_R {
+        ICACHE_PRELOCK_SCT1_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOCK_SCT1_ADDR")
+            .field("icache_prelock_sct1_addr", &self.icache_prelock_sct1_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct1_addr(
+        &mut self,
+    ) -> ICACHE_PRELOCK_SCT1_ADDR_W<ICACHE_PRELOCK_SCT1_ADDR_SPEC> {
+        ICACHE_PRELOCK_SCT1_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOCK_SCT1_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOCK_SCT1_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_prelock_sct1_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOCK_SCT1_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_prelock_sct1_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOCK_SCT1_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOCK_SCT1_ADDR to value 0"]
+impl crate::Resettable for ICACHE_PRELOCK_SCT1_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_prelock_sct_size.rs

@@ -0,0 +1,66 @@
+#[doc = "Register `ICACHE_PRELOCK_SCT_SIZE` reader"]
+pub type R = crate::R<ICACHE_PRELOCK_SCT_SIZE_SPEC>;
+#[doc = "Register `ICACHE_PRELOCK_SCT_SIZE` writer"]
+pub type W = crate::W<ICACHE_PRELOCK_SCT_SIZE_SPEC>;
+#[doc = "Field `ICACHE_PRELOCK_SCT1_SIZE` reader - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
+pub type ICACHE_PRELOCK_SCT1_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `ICACHE_PRELOCK_SCT1_SIZE` writer - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
+pub type ICACHE_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `ICACHE_PRELOCK_SCT0_SIZE` reader - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
+pub type ICACHE_PRELOCK_SCT0_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `ICACHE_PRELOCK_SCT0_SIZE` writer - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
+pub type ICACHE_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct1_size(&self) -> ICACHE_PRELOCK_SCT1_SIZE_R {
+        ICACHE_PRELOCK_SCT1_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct0_size(&self) -> ICACHE_PRELOCK_SCT0_SIZE_R {
+        ICACHE_PRELOCK_SCT0_SIZE_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_PRELOCK_SCT_SIZE")
+            .field("icache_prelock_sct1_size", &self.icache_prelock_sct1_size())
+            .field("icache_prelock_sct0_size", &self.icache_prelock_sct0_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct1_size(
+        &mut self,
+    ) -> ICACHE_PRELOCK_SCT1_SIZE_W<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
+        ICACHE_PRELOCK_SCT1_SIZE_W::new(self, 0)
+    }
+    #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
+    #[inline(always)]
+    pub fn icache_prelock_sct0_size(
+        &mut self,
+    ) -> ICACHE_PRELOCK_SCT0_SIZE_W<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
+        ICACHE_PRELOCK_SCT0_SIZE_W::new(self, 16)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_PRELOCK_SCT_SIZE_SPEC;
+impl crate::RegisterSpec for ICACHE_PRELOCK_SCT_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_prelock_sct_size::R`](R) reader structure"]
+impl crate::Readable for ICACHE_PRELOCK_SCT_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_prelock_sct_size::W`](W) writer structure"]
+impl crate::Writable for ICACHE_PRELOCK_SCT_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_PRELOCK_SCT_SIZE to value 0"]
+impl crate::Resettable for ICACHE_PRELOCK_SCT_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_sync_addr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ICACHE_SYNC_ADDR` reader"]
+pub type R = crate::R<ICACHE_SYNC_ADDR_SPEC>;
+#[doc = "Register `ICACHE_SYNC_ADDR` writer"]
+pub type W = crate::W<ICACHE_SYNC_ADDR_SPEC>;
+#[doc = "Field `ICACHE_SYNC_ADDR` reader - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
+pub type ICACHE_SYNC_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_SYNC_ADDR` writer - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
+pub type ICACHE_SYNC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
+    #[inline(always)]
+    pub fn icache_sync_addr(&self) -> ICACHE_SYNC_ADDR_R {
+        ICACHE_SYNC_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_SYNC_ADDR")
+            .field("icache_sync_addr", &self.icache_sync_addr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
+    #[inline(always)]
+    pub fn icache_sync_addr(&mut self) -> ICACHE_SYNC_ADDR_W<ICACHE_SYNC_ADDR_SPEC> {
+        ICACHE_SYNC_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_SYNC_ADDR_SPEC;
+impl crate::RegisterSpec for ICACHE_SYNC_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_sync_addr::R`](R) reader structure"]
+impl crate::Readable for ICACHE_SYNC_ADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_sync_addr::W`](W) writer structure"]
+impl crate::Writable for ICACHE_SYNC_ADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_SYNC_ADDR to value 0"]
+impl crate::Resettable for ICACHE_SYNC_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_sync_ctrl.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `ICACHE_SYNC_CTRL` reader"]
+pub type R = crate::R<ICACHE_SYNC_CTRL_SPEC>;
+#[doc = "Register `ICACHE_SYNC_CTRL` writer"]
+pub type W = crate::W<ICACHE_SYNC_CTRL_SPEC>;
+#[doc = "Field `ICACHE_INVALIDATE_ENA` reader - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+pub type ICACHE_INVALIDATE_ENA_R = crate::BitReader;
+#[doc = "Field `ICACHE_INVALIDATE_ENA` writer - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+pub type ICACHE_INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_SYNC_DONE` reader - The bit is used to indicate invalidate operation is finished."]
+pub type ICACHE_SYNC_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+    #[inline(always)]
+    pub fn icache_invalidate_ena(&self) -> ICACHE_INVALIDATE_ENA_R {
+        ICACHE_INVALIDATE_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to indicate invalidate operation is finished."]
+    #[inline(always)]
+    pub fn icache_sync_done(&self) -> ICACHE_SYNC_DONE_R {
+        ICACHE_SYNC_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_SYNC_CTRL")
+            .field("icache_invalidate_ena", &self.icache_invalidate_ena())
+            .field("icache_sync_done", &self.icache_sync_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
+    #[inline(always)]
+    pub fn icache_invalidate_ena(&mut self) -> ICACHE_INVALIDATE_ENA_W<ICACHE_SYNC_CTRL_SPEC> {
+        ICACHE_INVALIDATE_ENA_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_SYNC_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_SYNC_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_sync_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_SYNC_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_sync_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_SYNC_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_SYNC_CTRL to value 0x01"]
+impl crate::Resettable for ICACHE_SYNC_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/extmem/icache_sync_size.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ICACHE_SYNC_SIZE` reader"]
+pub type R = crate::R<ICACHE_SYNC_SIZE_SPEC>;
+#[doc = "Register `ICACHE_SYNC_SIZE` writer"]
+pub type W = crate::W<ICACHE_SYNC_SIZE_SPEC>;
+#[doc = "Field `ICACHE_SYNC_SIZE` reader - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
+pub type ICACHE_SYNC_SIZE_R = crate::FieldReader<u32>;
+#[doc = "Field `ICACHE_SYNC_SIZE` writer - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
+pub type ICACHE_SYNC_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
+impl R {
+    #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
+    #[inline(always)]
+    pub fn icache_sync_size(&self) -> ICACHE_SYNC_SIZE_R {
+        ICACHE_SYNC_SIZE_R::new(self.bits & 0x007f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_SYNC_SIZE")
+            .field("icache_sync_size", &self.icache_sync_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
+    #[inline(always)]
+    pub fn icache_sync_size(&mut self) -> ICACHE_SYNC_SIZE_W<ICACHE_SYNC_SIZE_SPEC> {
+        ICACHE_SYNC_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_SYNC_SIZE_SPEC;
+impl crate::RegisterSpec for ICACHE_SYNC_SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_sync_size::R`](R) reader structure"]
+impl crate::Readable for ICACHE_SYNC_SIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_sync_size::W`](W) writer structure"]
+impl crate::Writable for ICACHE_SYNC_SIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_SYNC_SIZE to value 0"]
+impl crate::Resettable for ICACHE_SYNC_SIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/extmem/icache_tag_power_ctrl.rs

@@ -0,0 +1,83 @@
+#[doc = "Register `ICACHE_TAG_POWER_CTRL` reader"]
+pub type R = crate::R<ICACHE_TAG_POWER_CTRL_SPEC>;
+#[doc = "Register `ICACHE_TAG_POWER_CTRL` writer"]
+pub type W = crate::W<ICACHE_TAG_POWER_CTRL_SPEC>;
+#[doc = "Field `ICACHE_TAG_MEM_FORCE_ON` reader - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
+pub type ICACHE_TAG_MEM_FORCE_ON_R = crate::BitReader;
+#[doc = "Field `ICACHE_TAG_MEM_FORCE_ON` writer - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
+pub type ICACHE_TAG_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_TAG_MEM_FORCE_PD` reader - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down"]
+pub type ICACHE_TAG_MEM_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `ICACHE_TAG_MEM_FORCE_PD` writer - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down"]
+pub type ICACHE_TAG_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ICACHE_TAG_MEM_FORCE_PU` reader - The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up"]
+pub type ICACHE_TAG_MEM_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `ICACHE_TAG_MEM_FORCE_PU` writer - The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up"]
+pub type ICACHE_TAG_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn icache_tag_mem_force_on(&self) -> ICACHE_TAG_MEM_FORCE_ON_R {
+        ICACHE_TAG_MEM_FORCE_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down"]
+    #[inline(always)]
+    pub fn icache_tag_mem_force_pd(&self) -> ICACHE_TAG_MEM_FORCE_PD_R {
+        ICACHE_TAG_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up"]
+    #[inline(always)]
+    pub fn icache_tag_mem_force_pu(&self) -> ICACHE_TAG_MEM_FORCE_PU_R {
+        ICACHE_TAG_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ICACHE_TAG_POWER_CTRL")
+            .field("icache_tag_mem_force_on", &self.icache_tag_mem_force_on())
+            .field("icache_tag_mem_force_pd", &self.icache_tag_mem_force_pd())
+            .field("icache_tag_mem_force_pu", &self.icache_tag_mem_force_pu())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
+    #[inline(always)]
+    pub fn icache_tag_mem_force_on(
+        &mut self,
+    ) -> ICACHE_TAG_MEM_FORCE_ON_W<ICACHE_TAG_POWER_CTRL_SPEC> {
+        ICACHE_TAG_MEM_FORCE_ON_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down"]
+    #[inline(always)]
+    pub fn icache_tag_mem_force_pd(
+        &mut self,
+    ) -> ICACHE_TAG_MEM_FORCE_PD_W<ICACHE_TAG_POWER_CTRL_SPEC> {
+        ICACHE_TAG_MEM_FORCE_PD_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up"]
+    #[inline(always)]
+    pub fn icache_tag_mem_force_pu(
+        &mut self,
+    ) -> ICACHE_TAG_MEM_FORCE_PU_W<ICACHE_TAG_POWER_CTRL_SPEC> {
+        ICACHE_TAG_MEM_FORCE_PU_W::new(self, 2)
+    }
+}
+#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_tag_power_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_tag_power_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ICACHE_TAG_POWER_CTRL_SPEC;
+impl crate::RegisterSpec for ICACHE_TAG_POWER_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`icache_tag_power_ctrl::R`](R) reader structure"]
+impl crate::Readable for ICACHE_TAG_POWER_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`icache_tag_power_ctrl::W`](W) writer structure"]
+impl crate::Writable for ICACHE_TAG_POWER_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ICACHE_TAG_POWER_CTRL to value 0x05"]
+impl crate::Resettable for ICACHE_TAG_POWER_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x05;
+}